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PDF AD7298 Data sheet ( Hoja de datos )
| Número de pieza | AD7298 | |
| Descripción | 12-Bit SAR ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Preliminary Technical Data
8-Channel, 1MSPS, 12-Bit SAR ADC
with Temperature Sensor
AD7298
FEATURES
12 bit SAR ADC
8 single-ended inputs
Channel sequencer functionality
Fast throughput of 1Msps
Analog Input Range 0 to 2.5V
12-bit temperature-to-digital converter
Temperature sensor accuracy of ±2°C typical
Temperature range: −40°C to +125°C
Specified for VDD of 2.8 V to 3.6V
Logic Voltage VDRIVE = 1.65V to 3.6V
Power-down current : <10 µA
Internal 2.5V Reference
Internal Power on Reset
High speed serial interface SPI™
20-lead LFCSP
GENERAL DESCRIPTION
The AD7298 is a 12-bit, high speed, low power, 8-channel,
successive approximation ADC with an internal temperature
sensor. The part operates from a single 3.3V power supply and
features throughput rates up to 1MSPS. The device contains a
low noise, wide bandwidth track-and-hold amplifier that can
handle input frequencies in excess of 70 MHz.
The AD7298 offers a programmable sequencer, which enables
the selection of a pre-programmable sequence of channels for
www.DacotanSvheerseito4nU..cTohme device has an on-chip 2.5 V reference that can be
disabled to allow the use of an external reference.
The AD7298 includes a high accuracy band-gap temperature
sensor, which is monitored and digitized by the12-bit ADC to
give a resolution of 0.25°C. The device offers a 4-wire serial
interface compatible with SPI, and DSP interface standards.
The AD7298 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. The part also
offers flexible power/throughput rate management options. The
part is offered in a 20 lead LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
PRODUCT HIGHLIGHTS
1. Ideally suited to monitoring system variables in a variety of
systems including telecommunications, process and
industrial control.
1. High Throughput rate of 1Msps per channel with Low
Power Consumption.
2. Eight Single-Ended Inputs with a Channel Sequencer.
A consecutive sequence of channels can be selected on
which the ADC cycles and converts.
3. Integrated temperature sensor with 0.25°C resolution.
Table 1. AD7298 and Related Products
Device Resolution Interface Features
AD7298 12-Bit SPI 8 Channel ADC & Temp Sensor
AD7291 12-Bit I2C 8 Channel ADC & Temp Sensor
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,nor for anyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
VDD to AGND, DGND,
VDRIVE to AGND, DGND,
Analog Input Voltage to AGND
Digital Input Voltage to AGND
Digital Output Voltage to AGND
VREF to AGND
AGND to DGND
Input Current to Any Pin Except
Supplies1
Operating Temperature Range
Storage Temperature Range
Junction Temperature
LFCSP Package
θJA Thermal Impedance
θJC Thermal Impedance
Pb-free Temperature, Soldering
Reflow
ESD
Rating
−0.3 V to +5 V
−0.3 V to + 5 V
−0.3 V to 3V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to +3V
−0.3 V to +0.3V
±10 mA
−40°C to +125°C
−65°C to +150°C
150°C
TBD°C/W
TBD°C/W
260(+0)°C
2 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
www.DadteavSicheeeret4liUa.bciolimty.
ESD CAUTION
AD7298
Rev. PrA | Page 5 of 18
5 Page 
Preliminary Technical Data
POWER-DOWN MODES
The AD7298 has a number of power conservation modes of
operation, which are designed to provide flexible power
management options. These options can be chosen to optimize
the power dissipation/throughput rate ratio for different
application requirements. The power-down modes of operation
of the AD7298 is controlled by the power-down bit, in the
control register and the PD pin on the device. When power
supplies are first applied to the AD7298, care should be taken to
ensure that the part is placed in the required mode of operation
NORMAL MODE
This mode is intended for the fastest throughput rate perform-
ance because the user does not have to worry about any power-
up times with the AD7298 remaining fully powered at all times.
Figure 6 shows the general diagram of the operation of the
AD7298 in this mode. The conversion is initiated on the falling
edge of CS and the track-and-hold enters hold mode. On the14th
SCLK falling edge the track-and-hold returns to track mode
and starts acquiring the analog input, as described in the serial
interface section. The data presented to the AD7298 on the DIN
line during the first 16 clock cycles of the data transfer are
loaded into the control register (provided the WRITE bit is 1).
The part remains fully powered up in normal mode at the end
of the conversion as long as PD bit is set to 0 in the write transfer
during that conversion. To ensure continued operation in
normal mode, the PD bit should be loaded with 0 on every data
write operation. Sixteen serial clock cycles are required to
complete the conversion and access the conversion result.
For specified performance, the throughput rate should not
exceed 1MSPS. Once a conversion is complete and the CS has
www.DaretatuSrhneeedt4hUi.gcho,ma minimum of the quiet time, tQUIET, must elapse
before bringing CS low again to initiate another conversion and
access the previous conversion result.
AD7298
Figure 6. Normal Mode Operation
PARTIAL POWER DOWN MODE
In this mode, part of the internal circuitry on the AD7298 is
powered-down. The AD7298 enters partial power-down on the
CS rising edge once the current serial write operation
containing 16 SCLK clock cycles is completed. To enter partial
power-down the PD bit in the control register should be set to
one on the last required read transfer from the AD7298. Once
in partial power-down mode the AD7298 transmits all ones on
the DOUT pin if CS is toggled low. If the averaging feature for the
temperature sensor is enabled in the control register, the
averaging is reset once the device enters partial power-down
mode.
The AD7298 remains in partial power-down until the power-
down bit, PD, in the control register is changed to a logic level
zero (0). The AD7298 begins powering up on the rising edge of
CS following the write to the control register disabling the
power-down bit. Once TQUITE has elapsed, a full 16-SCLK write
to the control register must be completed to update its content
with the desired channel configuration for the subsequent
conversion. A valid conversion is then initiated on the next CS
falling edge. Since the AD7298 has once cycle latency, the first
conversion result after exiting partial power-down mode is
available in the fourth serial transfer as shown in Figure 7; 1st
cycle to update PD bit, 2nd cycle to update configuration and
Channel ID bits, 3rd to complete conversion, 4th access DOUT
valid result. The use of this mode enables a reduction in the
overall power consumption of the device.
Rev. PrA | Page 11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AD7298.PDF ] | |
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