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ADP3211A Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer ADP3211A
Beschreibung Synchronous Buck Controller
Hersteller ON Semiconductor
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Gesamt 32 Seiten
ADP3211A Datasheet, Funktion
ADP3211, ADP3211A
7-Bit, Programmable,
Single-Phase, Synchronous
Buck Controller
The ADP3211 is a highly efficient, singlephase, synchronous
buck switching regulator controller. With its integrated driver, the
ADP3211 is optimized for converting the notebook battery voltage to
the supply voltage required by high performance Intel chipsets. An
internal 7bit DAC is used to read a VID code directly from the
chipset or the CPU and to set the GMCH render voltage or the CPU
core voltage to a value within the range of 0 V to 1.5 V.
The ADP3211 uses a multimode architecture. It provides
programmable switching frequency that can be optimized for
efficiency depending on the output current requirement. In addition,
the ADP3211 includes a programmable load line slope function to
adjust the output voltage as a function of the load current so that the
core voltage is always optimally positioned for a load transient. The
ADP3211 also provides accurate and reliable current overload
protection and a delayed powergood output. The IC supports
onthefly (OTF) output voltage changes requested by the chipset.
The ADP3211 has a boot voltage of 1.1 V for IMVP6.5
applications in CPU mode. The ADP3211A has a boot voltage of
1.2 V in CPU mode.
The ADP3211 is specified over the extended commercial temperature
range of 10°C to 100°C and is available in a 32lead QFN.
Features
SingleChip Solution
Fully Compatible with the Intel® IMVP6.5t CPU and GMCH
Chipset Voltage Regulator Specifications Integrated MOSFET
Drivers
Input Voltage Range of 3.3 V to 22 V
www.DataS±he7emt4UV.cWomorstCase Differentially Sensed Core Voltage Error
Overtemperature
Automatic PowerSaving Modes Maximize Efficiency During
Light Load Operation
Soft Transient Control Reduces Inrush Current and Audio Noise
Independent Current Limit and Load Line Setting Inputs for
Additional Design Flexibility
Builtin PowerGood Masking Supports Voltage Identification
(VID) OTF Transients
7Bit, Digitally Programmable DAC with 0 V to 1.5 V Output
ShortCircuit Protection
Current Monitor Output Signal
This is a PbFree Device
Fully RoHS Compliant
32Lead QFN
Applications
Notebook Power Supplies for Next Generation Intel Chipsets
Intel Netbook Atom Processors
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1 32
QFN32
MN SUFFIX
CASE 488AM
MARKING DIAGRAM
1
xxxxxx
xxxxxx
AWLYYWW
xxx = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN ASSIGNMENT
PWRGD
IMON
CLKEN
FBRTN
FB
COMP
GPU
ILIM
1
ADP3211
ADP3211A
(top view)
VCC
BST
DRVH
SW
PVCC
DRVL
PGND
GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 31 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
April, 2009 Rev. 0
1
Publication Order Number:
ADP3211/D






ADP3211A Datasheet, Funktion
ADP3211, ADP3211A
ELECTRICAL CHARACTERISTICS (VCC = PVCC = 5.0 V, FBRTN = GND = PGND = 0 V, H = 5.0 V, L = 0 V, VVID = VDAC = 1.2 V,
TA = 10°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sunk by the device) has a positive sign.
Parameter
Symbol
Conditions
Min Typ Max Units
VOLTAGE MONITORING and PROTECTION Power Good
PWRGD High Leakage
Current
IPWRGD
VPWRDG = 5.0 V
1.0 mA
PWRGD Startup Delay
TSSPWRGD
Measured from CLKEN neg edge to PWRGD
pos edge
8.0
ms
PWRGD Latchoff Delay
TLOFFPWRGD
Measured from OutoffGoodWindow event
to Latchoff (switching stops)
8.0
ms
PWRGD Propagation Delay
(Note 2)
TPDPWRGD
Measured from OutoffGoodWindow event
to PWRGD neg edge
200
ns
Crowbar Latchoff Delay
(Note 2)
TLOFFCB
Measured from Crowbar event to Latchoff
(switching stops)
200 ns
PWRGD Masking Time
CSREF SoftStop Resistance
TMSkPWRGD
Triggered by any VID change
EN = L or Latchoff condition
CURRENT CONTROL Current Sense Amplifier (CSAMP)
100 ms
60 W
CSFB, CSREF CommonMode Range
(Note 2)
Voltage range of interest
0 2.0 V
CSFB, CSREF Offset Voltage
CSFB Bias Current
CSREF Bias Current
CSCOMP Voltage Range
(Note 2)
VOSCSA
IBCSFB
IBCSREF
CSREF – CSSUM, TA = 0°C to 85°C
TA = 25°C
Voltage range of interest
1.4
0.4
50
2.0
0.05
+1.4 V
+0.4
+50 nA
2.0 mA
2.0 V
CSCOMP Current
CSCOMP Slew Rate (Note 2)
ICSCOMPsource
ICSCOMPsink
CSCOMP = 2.0 V
CSFB forced 200 mV below CSREF
CSFB forced 200 mV above CSREF
CCSCOMP = 10 pF, CSREF = VDAC,
Open loop configuration
CSFB forced 200 mV below CSREF
CSFB forced 200 mV above CSREF
650
1.0
10
10
mA
mA
V/ms
Gain Bandwidth (Note 2)
GBWCSA
Noninverting unit gain configuration
RFB = 1 kW
www.DataSChUeReRt4EUN.cToMmONITORING AND PROTECTION Current Reference
IREF Voltage
VREF
RREF = 80 kW to set IREF = 20 mA
CURRENT LIMITER (OCP)
Current Limit (OCP)
Threshold
VLIMTH
Measured from CSCOMP to CSREF
RLIM = 4.5 kW
Current Limit Latchoff Delay
Measured from OCP event to PWRGD
deassertion
20 MHz
1.55 1.6 1.65
V
130 100
8.0
70
mV
ms
CURRENT MONITOR
Current Gain Accuracy
IMON/ILIM
Measured from ILIM to IMON
ILIM = 20 mA
ILIM = 10 mA
ILIM = 5 mA
9.5 10
9.4 10
9.0 10
IMON Clamp Voltage
VMAXMON
Relative to FBRTN, ILIM = 30 mA
RIMON = 8 kW
1.0
1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
10.6
10.8
11
1.15
V
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6

6 Page









ADP3211A pdf, datenblatt
ADP3211, ADP3211A
Theory of Operation
The ADP3211 is a Ramp Pulse Modulated (RPM)
controller for synchronous buck Intel GMCH and CPU core
power supply. The internal 7bit VID DAC conforms to the
Intel IMVP6.5 specifications. The ADP3211 is a stable,
high performance architecture that includes
High speed response at the lowest possible switching
frequency and minimal count of output decoupling
capacitors
Minimized thermal switching losses due to lower
frequency operation
High accuracy load line regulation
High power conversion efficiency with a light load by
automatically switching to DCM operation
Operation Modes
The ADP3211 runs in RPM mode for the purpose of fast
transient response and high light load efficiency. During
the following transients, the ADP3211 runs in PWM mode:
SoftStart
Soft transient: the period of 110 ms following any VID
change
Current overload
IR = AR X IRAMP
VRMP
FLIPFLOP
SQ
RD
CR
1.0 V
400ns FLIPFLOP
Q SQ
Q
R2 RD
R1
5.0 V
BST1
GATE DRIVER
BST
IN
DRVH
SW
DCM DRVL
DRVH1
SW1
DRVL1
VCC
RI L
www.DataSheet4U.com
30mV
COMP
R2 R1
1.0 V
VDC
+ VCS
+
+
FB FBRTN LLINE CSCOMP
RA CA
CFB
CB
RB
CSREF
CSFB
RCS
CCS
Figure 19. RPM Mode Operation
RPH
LOAD
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