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PDF AD6653 Data sheet ( Hoja de datos )
| Número de pieza | AD6653 | |
| Descripción | IF Diversity Receiver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD6653 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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IF Diversity Receiver
AD6653
FEATURES
SNR = 70.8 dBc (71.8 dBFS) in a 32.7 MHz BW at
70 MHz @ 150 MSPS
SFDR = 83 dBc to 70 MHz @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS
output supply
Integer 1-to-8 input clock divider
Integrated dual-channel ADC
Sample rates up to 150 MSPS
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Integrated wideband digital downconverter (DDC)
32-bit, complex, numerically controlled oscillator (NCO)
Decimating half-band filter and FIR filter
Supports real and complex output modes
Fast attack/threshold detect bits
Composite signal monitor
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA,
CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
PRODUCT HIGHLIGHTS
1. Integrated dual, 12-bit, 125 MSPS/150 MSPS ADC.
2. Integrated wideband decimation filter and 32-bit
complex NCO.
3. Fast overrange detect and signal monitor with serial output.
4. Proprietary differential input maintains excellent SNR
performance for input frequencies up to 450 MHz.
5. Flexible output modes, including independent CMOS,
interleaved CMOS, IQ mode CMOS, and interleaved LVDS.
6. SYNC input allows synchronization of multiple devices.
7. 3-bit SPI port for register programming and register readback.
AVDD
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VIN+A
VIN–A
SHA
FUNCTIONAL BLOCK DIAGRAM
FD[0:3]A
DVDD
FD BITS/THRESHOLD
DETECT
ADC
I
LP/HP
DECIMATING
HB FILTER +
Q FIR
DRVDD
AD6653
D11A
D0A
VREF
SENSE
CML
RBIAS
REF
SELECT
VIN–B
VIN+B
SHA
SIGNAL
MONITOR
ADC
32-BIT
TUNING
NCO
Q
LP/HP
DECIMATING
HB FILTER +
I FIR
fADC/8
NCO
DIVIDE 1
TO 8
DUTY
CYCLE
STABILIZER
DCO
GENERATION
PROGRAMMING DATA
MULTI-CHIP
SYNC
FD BITS/THRESHOLD SIGNAL MONITOR
DETECT
DATA
SIGNAL MONITOR
INTERFACE
SPI
CLK+
CLK–
DCOA
DCOB
D11B
D0B
AGND SYNC
FD[0:3]B
SMI SMI SMI
SDIO/ SCLK/ CSB
SDFS SCLK/ SDO/
DCS DFS
PDWN OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 10 FOR LVDS PIN NAMES.
DRGND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
AD6653
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance1
VREF INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD, DVDD
DRVDD (CMOS Mode)
www.DataShDeReVt4DUD.c(oLmVDS Mode)
Supply Current
IAVDD 2 , 3
IDVDD2, 3
IDRVDD2 (3.3 V CMOS)
IDRVDD2 (1.8 V CMOS)
IDRVDD2 (1.8 V LVDS)
POWER CONSUMPTION
DC Input
Sine Wave Input2 (DRVDD = 1.8 V)
Sine Wave Input2 (DRVDD = 3.3 V)
Standby Power4
Power-Down Power
Temperature
Full
Full
Full
Full
25°C
25°C
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD6653BCPZ-125
Min Typ
Max
12
Guaranteed
±0.3 ±0.6
−3.9 −2.7
−0.7
±0.3 ±0.6
±0.1 ±0.7
±19
±38
±5 ±18
7
0.21
2
8
6
1.7 1.8
1.7 3.3
1.7 1.8
390
270
20
12
57
770
1215
1275
77
2.5
1.9
3.6
1.9
689
800
8
AD6653BCPZ-150
Min Typ Max
12
Guaranteed
±0.2 ±0.6
−5.2 −3.2 −0.9
±0.2 ±0.7
±0.2 ±0.7
±17
±49
±5 ±18
7
0.21
2
8
6
1.7 1.8 1.9
1.7 3.3 3.6
1.7 1.8 1.9
440
320 785
24
15
57
870
1395
1450
77
2.5
905
8
Unit
Bits
% FSR
% FSR
% FSR
% FSR
ppm/°C
ppm/°C
mV
mV
LSB rms
V p-p
pF
kΩ
V
V
V
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
1 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 11 for the equivalent analog input structure.
2 Measured with a 9.7 MHz, full-scale sine wave input, NCO enabled with a frequency of 13 MHz, FIR filter enabled and the fS/8 output mix enabled with approximately
5 pF loading on each output bit.
3 The maximum limit applies to the combination of IAVDD and IDVDD currents.
4 Standby power is measured with a dc input and with the CLK pin inactive (set to AVDD or AGND).
Rev. 0 | Page 5 of 80
5 Page 
CLK+
DECIMATED
INTERLEAVED
CMOS DATA
DECIMATED
INTERLEAVED
FD DATA
DECIMATED
DCO
tPD
CHANNEL A:
DATA
CHANNEL A:
FD BITS
CHANNEL B:
DATA
CHANNEL B:
FD BITS
CHANNEL A:
DATA
CHANNEL A:
FD BITS
tS
tH
CHANNEL B:
DATA
CHANNEL B:
FD BITS
tDCO
CHANNEL A:
DATA
CHANNEL A:
FD BITS
CHANNEL B:
DATA
CHANNEL B:
FD BITS
Figure 4. Decimated Interleaved CMOS Mode Data and Fast Detect Output Timing
AD6653
CLK+
DECIMATED
CMOS IQ
OUTPUT DATA
CMOS FD
DATA
DECIMATED
DCOA/DCOB
tPD
CHANNEL A/B:
Q DATA
CHANNEL A/B:
I DATA
CHANNEL A/B:
Q DATA
tDCO
CHANNEL A/B:
I DATA
CHANNEL A/B:
Q DATA
CHANNEL A/B:
I DATA
CHANNEL A/B:
FD BITS
CHANNEL A/B:
FD BITS
tS
tH
CHANNEL A/B:
FD BITS
CHANNEL A/B:
FD BITS
CHANNEL A/B:
FD BITS
Figure 5. Decimated IQ Mode CMOS Data and Fast Detect Output Timing
CHANNEL A/B:
FD BITS
CLK–
CLK+
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LVDS
DATA
LVDS
FAST DET
DCO–
DCO+
tPD
CHANNEL A:
DATA
CHANNEL A:
FD
CHANNEL B:
DATA
CHANNEL B:
FD
CHANNEL A:
DATA
CHANNEL A:
FD
tDCO
CHANNEL B:
DATA
CHANNEL B:
FD
CHANNEL A:
DATA
CHANNEL A:
FD
Figure 6. Decimated Interleaved LVDS Mode Data and Fast Detect Output Timing
CLK+
SYNC
tSSYNC
tHSYNC
Figure 7. SYNC Timing Inputs
Rev. 0 | Page 11 of 80
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD6653.PDF ] | |
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