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ADP5587 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP5587
Beschreibung Mobile I/O Expander And QWERTY Keypad Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
ADP5587 Datasheet, Funktion
FEATURES
18-GPIO port expander or 10 × 8 keypad matrix
GPIOs configurable as GPIs, GPOs, and keypad rows or
columns
I2C interface with auto-increment
1.7 V to 3.6 V operation
Keypad lock capability
Open-drain interrupt output
Key press and key release interrupts
GPI interrupt with level programmability
Programmable pull-ups
Key event counter with overflow interrupt
275 μs debounce on the reset line and GPIs
1 μA typical idle current
55 μA typical polling current
Small 4 mm × 4 mm LFCSP package
APPLICATIONS
Keypad and I/O expander designed for QWERTY type phones
that require a large keypad matrix
GENERAL DESCRIPTION
The ADP5587 is an I/O port expander and keypad matrix
designed for QWERTY type phones that require a large keypad
matrix and expanded I/O lines. I/O expander ICs are used in
mobile platforms as a solution to the limited number of GPIOs
available in the main processor.
In its small 4 mm × 4 mm package, the ADP5587 contains
www.DaentaoSuhgehetp4oUw.ceormto handle all key-scanning and decoding and
to flag the processor of key presses and releases via the I2C
interface and interrupt. The ADP5587 frees the main micro-
processor from the need to monitor the keypad, thereby
minimizing current drain and increasing processor bandwidth.
The ADP5587 is also equipped with a buffer/FIFO and key
event counter to handle and keep track of up to 10 unprocessed
key or GPI events with overflow wrap and interrupt capability.
Mobile I/O Expander and
QWERTY Keypad Controller
ADP5587
FUNCTIONAL BLOCK DIAGRAM
ADP5587
GND 19
VCC 21
SCL 23
SDA 22
RST 20
INT 24
CONTROL
REGISTERS
CONTROL
INTERFACE
C9
18
C8
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure 1.
The ADP5587 has keypad lock capability with an option to
trigger or not trigger an interrupt at key presses and releases.
All communication to the main processor is done using one
interrupt line and two I2C-compatible interface lines. The
ADP5587 can be configured as a keypad matrix of up to 8 rows ×
10 columns (a maximum of 80 keys).
When the ADP5587 is used for smaller keypad matrices, unused
row and column pins can be reconfigured to act as general-
purpose inputs or outputs. R0 to R7 denote the row pins of the
matrix, whereas C0 to C9 denote the column pins. At power-up,
all rows and columns default to GPIs and must be programmed
to function as part of the keypad matrix or as GPOs.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.






ADP5587 Datasheet, Funktion
ADP5587
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
R7 1
R6 2
R5 3
R4 4
R3 5
R2 6
PIN 1
INDICATOR
ADP5587
TOP VIEW
(Not to Scale)
18 C9
17 C8
16 C7
15 C6
14 C5
13 C4
NOTES
1. EXPOSED PAD MUST BE CONNECTED TO GROUND.
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic
Description
1 R7
GPIO, Row 7 in the Keypad Matrix.
2 R6
GPIO, Row 6 in the Keypad Matrix.
3 R5
GPIO, Row 5 in the Keypad Matrix.
4 R4
GPIO, Row 4 in the Keypad Matrix.
5 R3
GPIO, Row 3 in the Keypad Matrix.
6 R2
GPIO, Row 2 in the Keypad Matrix.
7 R1
GPIO, Row 1 in the Keypad Matrix.
8 R0
GPIO, Row 0 in the Keypad Matrix.
9 C0
GPIO, Column 0 in the Keypad Matrix.
10 C1
GPIO, Column 1 in the Keypad Matrix.
11 C2
GPIO, Column 2 in the Keypad Matrix.
12 C3
GPIO, Column 3 in the Keypad Matrix.
13 C4
GPIO, Column 4 in the Keypad Matrix.
14 C5
GPIO, Column 5 in the Keypad Matrix.
15 C6
GPIO, Column 6 in the Keypad Matrix.
16 C7
GPIO, Column 7 in the Keypad Matrix.
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GPIO, Column 8 in the Keypad Matrix.
18 C9
GPIO, Column 9 in the Keypad Matrix.
19 GND
Ground.
20 RST
Hardware Reset (Active Low). This pin resets the device to the power default conditions. The reset pin must
be driven low for a minimum of 50 μs to be valid and to prevent false resets due to ESD glitches or noise in
the system. If not used, RST must be tied high with a pull-up resistor.
21 VCC
22 SDA
Supply Voltage, 1.7 V to 3.6 V.
I2C Serial Data (Open Drain Requires External Pull-Up Resistor).
23 SCL
I2C Clock.
24 INT
Processor Interrupt, Active Low, Open Drain. This pin can be pulled up to 2.7 V or 1.8 V for selection flexibility
in the processor GPIO supply group.
EP EPAD
Exposed Pad. The exposed pad must be connected to ground.
Rev. 0 | Page 6 of 24

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ADP5587 pdf, datenblatt
ADP5587
275 Microsecond Interrupt Configuration
The ADP5587 gives the user the flexibility of deasserting the
interrupt for 275 μs while there is a pending event. When the
INT_CFG bit in Register 0x01 is set, any attempt to clear the
interrupt bit while the interrupt pin is already asserted results
in a 275 μs deassertion. When the INT_CFG bit is cleared, the
processor interrupt remains asserted if the host tries to clear
the interrupt. This feature is particularly useful for software
development and edge triggering applications.
Debouncing
The ADP5587 has a 275 μs debounce time for GPIOs configured
as GPIs and rows in keypad scanning mode. The reset line
always has a 275 μs debounce time.
Table 14. Device Configuration
Keypad
Matrix
Active Pins
10 × 8
C0 to C9, R0 to R7
8×8
C0 to C7, R0 to R7
8×7
C0 to C7, R0 to R6
8×6
C0 to C7, R0 to R5
8×5
C0 to C7, R0 to R4
7×7
C0 to C6, R0 to R6
7×6
C0 to C6, R0 to R5
7×5
C0 to C6, R0 to R4
6×6
C0 to C5, R0 to R5
6×5
C0 to C5, R0 to R4
6×4
C0 to C5, R0 to R3
……
0×0
None
www.DataSheet4U.com
Number of Keys
80
64
56
48
40
49
42
35
36
30
24
0
General-Purpose Outputs (GPOs)
The ADP5587 allows the user to configure all or some of its
GPIOs as GPOs. These GPOs can be used as extra enables for
the host processor or simply as trigger outputs. When configured
as an output (GPO), a digital buffer drives the pin to 0 V for a 0
and to VCC for a 1. To set any GPIO as a GPO, make sure that
the corresponding bits in Register 0x1D through Register 0x1F are
set for GPIO mode; then use Register 0x23 through Register 0x25
to set the corresponding bits for GPO mode.
Power-On Reset
For built-in power-up initialization for applications lacking a
power-on reset signal, a reset pin, RST, allows the user to reset
the registers to default values in the event of a brownout or
other reset condition.
Available GPIO
0
C8, C9
R7, C8, C9
R6, R7, C8, C9
R5 to R7, C8, C9
R7, C7 to C9
R6, R7, C7 to C9
R5 to R7, C7 to C9
R6, R7, C6 to C9
R5 to R7, C6 to C9
R4 to R7, C6 to C9
R0 to R7, C0 to C9
GPIO
Number of GPIOs
0
2
3
4
5
4
5
6
6
7
8
18
Rev. 0 | Page 12 of 24

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