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ADAU1381 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADAU1381
Beschreibung Low Noise Stereo Codec
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADAU1381 Datasheet, Funktion
Low Noise Stereo Codec with Enhanced
Recording and Playback Processing
ADAU1381
FEATURES
GENERAL DESCRIPTION
24-bit stereo audio ADC and DAC
400 mW speaker amplifier (into 8 Ω load)
Built-in sound engine for audio processing
Wind noise detection and autofiltering
Enhanced stereo capture (ESC)
The ADAU1381 is a low power, 24-bit stereo audio codec. The
low noise DAC and ADC support sample rates from 8 kHz to
96 kHz. Low current draw and power saving modes make the
ADAU1381 ideal for battery-powered audio applications.
Dual-band automatic level control (ALC)
A configurable sound engine provides enhanced record and
6-band equalizer, including notch filter
playback processing to improve overall audio quality.
Sampling rates from 8 kHz to 96 kHz
Stereo pseudo differential microphone input
Optional stereo digital microphone input pulse-density
modulation (PDM)
Stereo line output
PLL supporting a range of input clock rates
Analog and digital I/O 1.8 V to 3.3 V
Software control via SigmaStudio graphical user interface
The record path includes two digital stereo microphone inputs
and an analog stereo input path. The analog inputs can be
configured for either a pseudo differential or a single-ended
stereo source. A dedicated analog beep input signal can be
mixed into any output path. The ADAU1381 includes a stereo
line output and speaker driver, which makes the device capable of
supporting dynamic speakers.
Software-controllable, clickless mute
Software register and hardware pin standby mode
32-lead, 5 mm × 5 mm LFCSP or 30-ball, 6 × 5 bump WLCSP
The serial control bus supports the I2C® or SPI protocols, and
the serial audio bus is programmable for I2S, left-justified, right-
justified, or TDM mode. A programmable PLL supports flexible
APPLICATIONS
clock generation for all standard rates and available master clocks
Digital still cameras
from 11 MHz to 20 MHz.
Digital video cameras
FUNCTIONAL BLOCK DIAGRAM
www.DataSheet4U.com
BEEP
LMIC/LMICN/
MICD1
LMICP
RMIC/RMICN/
MICD2
RMICP
PDN
MICBIAS
PGA
PGA
PGA
MICROPHONE
BIAS
REGULATOR
ADAU1381
LEFT
ADC
RIGHT
ADC
SOUND ENGINE
DECIMATION
FILTERS
WIND NOISE
NOTCH FILTER
EQUALIZER
DIGITAL VOLUME
CONTROL
AUTOMATIC LEVEL
CONTROL
LEFT
DAC
RIGHT
DAC
OUTPUT
MIXER
PLL
SERIAL DATA
INPUT/OUTPUT PORTS
I2C/SPI
CONTROL PORT
AOUTL
AOUTR
SPP
SPN
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.






ADAU1381 Datasheet, Funktion
ADAU1381
Parameter
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Beep Input Mute Attenuation
Offset Error
Gain Error
Interchannel Gain Mismatch
Beep Input PGA Gain Range
Beep Playback Mixer Gain Range
Power Supply Rejection Ratio
MICROPHONE BIAS
Bias Voltage
0.65 × AVDD
0.90 × AVDD
Bias Current Source
Noise in the Signal Bandwidth
www.DataSheet4U.com
Test Conditions/Comments
−60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 3.3 V; mute set by
Register 0x4008, Bit 3
AVDD = 3.3 V
AVDD = 3.3 V
AVDD = 3.3 V
AVDD = 3.3 V
CM capacitor = 10 μF
AVDD = 3.3 V, 100 mV p-p at 217 Hz
AVDD = 3.3 V, 100 mV p-p at 1 kHz
Microphone bias enabled
AVDD = 1.8 V, low bias
AVDD = 3.3 V, low bias
AVDD = 1.8 V, high bias
AVDD = 3.3 V, high bias
AVDD = 3.3 V, high bias, high
performance
AVDD = 3.3 V, 20 Hz to 20 kHz
High bias, high performance
High bias, low performance
Low bias, high performance
Low bias, low performance
AVDD = 1.8 V, 20 Hz to 20 kHz
High bias, high performance
High bias, low performance
Low bias, high performance
Low bias, low performance
Min
−23
−15
OUTPUT SIDE PERFORMANCE SPECIFICATIONS
Specifications guaranteed at 25°C (ambient).
Table 2.
Parameter
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution
Digital Attenuation Step
Digital Attenuation Range
DAC TO LINE OUTPUT PATH
Full-Scale Output Voltage (0 dB)
Line Output Mute Attenuation,
DAC to Mixer Path Muted
Line Output Mute Attenuation,
Line Output Muted
Test Conditions/Comments
All DACs
Min
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 3.3 V; mute set by Register
0x401C, Bit 5, and Register 0x401E, Bit 6
AVDD = 3.3 V; mute set by Register
0x4025, Bit 1, and Register 0x4026, Bit 1
Rev. 0 | Page 6 of 84
Typ
99
105
96
102
−90
10
−0.3
30
−58
−72
1.17
2.145
1.62
2.97
39
78
25
35
35
45
23
23
Max
+32
+6
5
Typ Max
24
0.375
95
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
−85
−85
Unit
dB
dB
dB
dB
dB
mV
dB
mdB
dB
dB
dB
dB
V
V
V
V
mA
nV√Hz
nV√Hz
nV√Hz
nV√Hz
nV√Hz
nV√Hz
nV√Hz
nV√Hz
Unit
Bits
dB
dB
V rms
V rms (V p-p)
V rms (V p-p)
dB
dB

6 Page









ADAU1381 pdf, datenblatt
ADAU1381
Digital Timing Diagrams
tBIH
BCLK
LRCLK
tBIL
tLIS
DAC_SDATA
LEFT-JUSTIFIED
MODE
DAC_SDATA
I2S MODE
DAC_SDATA
RIGHT-JUSTIFIED
MODE
tSIS
MSB
tSIH
MSB – 1
tSIS
MSB
tSIH
8-BIT CLOCKS
(24-BIT DATA)
tSIS
MSB
tSIH
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Serial Input Port Timing
BCLK
tBIH
tBIL
www.DataSheet4LUR.CcLoKm
ADC_SDATA
LEFT-JUSTIFIED
MODE
ADC_SDATA
I2S MODE
ADC_SDATA
RIGHT-JUSTIFIED
MODE
tSODM
MSB
MSB – 1
tSODM
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
tSODM
MSB
Figure 3. Serial Output Port Timing
Rev. 0 | Page 12 of 84
tLIH
tSIS
LSB
tSIH
LSB

12 Page





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