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WCMA2016U4B Schematic ( PDF Datasheet ) - Weida Semiconductor

Teilenummer WCMA2016U4B
Beschreibung 128K x 16 Static RAM
Hersteller Weida Semiconductor
Logo Weida Semiconductor Logo 




Gesamt 12 Seiten
WCMA2016U4B Datasheet, Funktion
1*WCMA2016U4B
WCMA2016U4B
Features
• High Speed
— 55ns and 70ns speed availability
• Low Voltage range:
— 2.7V-3.3V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1MHz
— Typical active current: 7 mA @ f = fmax
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The WCMA2016U4B is a high-performance CMOS static
RAMs organized as 128K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active cur-
rent. This device is ideal for portable applications such as cel-
lular telephones. The devices also have an automatic pow-
er-down feature that significantly reduces power consumption
by 80% when addresses are not toggling. The device can also
128K x 16 Static RAM
be put into standby mode reducing power consumption by
more than 99% when deselected (CE HIGH or both BLE and
BHE are HIGH). The input/output pins (I/O0 through I/O15) are
placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), both Byte High En-
able and Byte Low Enable are disabled (BHE, BLE HIGH), or
during a write operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE ) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE ) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE ) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The WCMA2016U4B is available in a 48-ball FBGA package.
Logic Block Diagram
www.DataSheet4U.com
A 101 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
128K x 16
RAM Array
2048 x 1024
I/O0 – I/O7
I/O8 – I/O15
COLUMN DECODER
Powe r -Down
Circuit
CE
BHE
BLE
BHE
WE
CE
OE
BLE






WCMA2016U4B Datasheet, Funktion
WCMA2016U4B
Switching Waveforms
Read Cycle No. 1 (Address Transistion Controlled) [13, 14]
tRC
ADDRESS
tOHA
tAA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled) [14, 15]
ADDRESS
CE
OE
BHE/BLE
tACE
tDOE
ttLLZZOOEE
DATA OUT
VCC
www.DataShSeUetP4PUL.cYom
CURRENT
tDBE
tLZBE
HIGH IMPEDANCE
tLZCE
tPU
50%
tRC
DATA VALID
tPD
tHZCE
tHZOE
tHZBE
HIGH
IMPEDANCE
50%
ICC
ISB
Notes:
13. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident withCE, BHE, BLE transition LOW.
6

6 Page









WCMA2016U4B pdf, datenblatt
WCMA2016U4B
Document Title: WCMA2016U4B, 128K x 16 STATIC RAM
REV.
Spec #
ECN #
Issue Date
** 38-05320
117494
7/19/02
Orig. of Change Description of Change
CBD
New Datasheet
www.DataSheet4U.com
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SeitenGesamt 12 Seiten
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