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WCMA2008U1X Schematic ( PDF Datasheet ) - Weida Semiconductor

Teilenummer WCMA2008U1X
Beschreibung 256K x 8 Static RAM
Hersteller Weida Semiconductor
Logo Weida Semiconductor Logo 




Gesamt 11 Seiten
WCMA2008U1X Datasheet, Funktion
A2008U1X
WCMA2008U1X
Features
• High Speed
— 70ns availability
• Voltage range
— 2.7V–3.6V
• Ultra low active power
— Typical active current: 1 mA @ f = 1MHz
— Typical active current: 7 mA @ f = fmax (70ns speed)
• Low standby power
• Easy memory expansion with CE1,CE2,and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The WCMA2008U1X is a high-performance CMOS static
RAM organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is device is ideal for portable applications. The device also
has an automatic power-down feature that significantly reduc-
Logic Block Diagram
256K x 8 Static RAM
es power consumption by 80% when addresses are not tog-
gling. The device can be put into standby mode reducing pow-
er consumption by more than 99% when deselected (CE1
HIGH or CE2 LOW).
Writing to the device is accomplished by taking Chip Enable
(CE1) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE2) HIGH. Data on the eight I/O pins (I/O0 through I/O7) is
then written into the location specified on the address pins (A0
through A17).
Reading from the device is accomplished by taking Chip En-
able (CE1) and Output Enable (OE) LOW while forcing Write
Enable (WE) and Chip Enable 2 (CE2) HIGH. Under these
conditions, the contents of the memory location specified by
the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW and CE2 HIGH and WE
LOW).
The WCMA2008U1X is available in a 36-ball FBGA package.
www.DataSheet4U.com
AAA021
AAAAAAAAA11516890347
CE2 CE1
WE
OE
Data in Drivers
128K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7






WCMA2008U1X Datasheet, Funktion
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled) [9, 10]
ADDRESS
DATA OUT
tOHA
PREVIOUS DATA VALID
tAA
tRC
WCMA2008U1X
DATA VALID
Read Cycle No. 2 (OE Controlled)[10, 11]
ADDRESS
CE1
CE2
OE
DATA OUT
VCC
SUPPLY
CURRENT
tACE
tDOE
tLZOE
HIGH IMPEDANCE
tLZCE
tPU
50%
tRC
DATA VALID
tHZOE
tHZCE
HIGH
IMPEDANCE
tPD
50%
ICC
ISB
www.DatNaSothese:et4U.com
9. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
6

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