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PDF CG6457AM Data sheet ( Hoja de datos )
| Número de pieza | CG6457AM | |
| Descripción | (CG6457AM / CG6462AM) FAN Controller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PSoC™ Mixed-Signal Array
FAN Controller
CG6457AM and CG6462AM
Preliminary Data Sheet
Features
■ Excellent for Fan Control Applications
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 12 MHz
❐ Low Power at High Speed
❐ 4.75V to 5.25V Operating Voltage
❐ Extended Temperature Range:
-40°C to +125°C
■ Advanced Peripherals (PSoC Blocks)
❐ 4 Analog Type “E” PSoC Blocks Provide:
- 2 Comparators with DAC Refs
- Single or Dual 8-Bit 8:1 ADC
❐ 4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART, SPI™ Master or Slave
- Connectable to All GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Flexible On-Chip Memory
❐ 4K Flash Program Storage
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP™)
❐ Partial Flash Updates
❐ Flexible Protection Modes
■ Complete Development Tools
❐ Free Development Software
(PSoC™ Designer)
❐ Full-Featured, In-Circuit Emulator and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 Bytes Trace Memory
■ Precision, Programmable Clocking
❐ Internal ±3.5% 24 MHz Oscillator
❐ Internal Oscillator for Watchdog and Sleep
■ Programmable Pin Configurations
❐ 25 mA Drive on All GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open
Drain Drive Modes on All GPIO
❐ Up to 8 Analog Inputs on GPIO
❐ Configurable Interrupt on All GPIO
■ Additional System Resources
❐ I2C™ Master, Slave and Multi-Master to
400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
PSoC
CORE
SystemBus
Port 1 Port 0
Global Digital Interconnect
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Global Analog Interconnect
SRAM
Interrupt
Controller
SROM
Flash
CPU Cor e
(M8C)
Sleep and
Watchdog
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
Digital
PSoC Block
Array
ANALOG SYSTEM
Analog
PSoC Block
Array
Analog
Ref .
Digital
Clocks
POR and LVD
I2 C
System Resets
SYSTEM RESOURCES
Internal
Voltage
Ref .
PSoC™ Functional Overview
The PSoC™ family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable component. A
PSoC device includes configurable blocks of analog and digital
logic, as well as programmable interconnect. This architecture
allows the user to create customized peripheral configurations,
to match the requirements of each individual application. Addi-
tionally, a fast CPU, Flash program memory, SRAM data mem-
ory, and configurable IO are included in a range of convenient
pinouts.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow all the device resources to be combined into a
complete custom system. Each PSoC device includes four digi-
tal blocks. Depending on the PSoC package, up to two analog
comparators and up to 16 general purpose IO (GPIO) are also
included. The GPIO provide access to the global digital and
analog interconnects.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO (inter-
nal main oscillator) and ILO (internal low speed oscillator). The
May 24, 2005
© Cypress Semiconductor Corp. 2005 — Document No. 001-00353 Rev. **
1
1 page  
CG64xxAM Preliminary Data Sheet
PSoC™ Overview
PSoC Designer Software Subsystems
Device Editor
The device editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic reconfig-
uration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for
selected PSoC block configurations and creates source code
for an application framework. The framework contains software
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run time. PSoC Designer can print out a configuration sheet for
a given project configuration for use during application pro-
gramming in conjunction with the Device Data Sheet. Once the
framework is generated, the user can add application-specific
code to flesh out the framework. It’s also possible to change the
selected components and regenerate the framework.
Design Browser
The Design Browser allows users to select and import precon-
figured designs into the user’s project. Users can easily browse
a catalog of preconfigured designs to facilitate time-to-design.
Examples provided in the tools include a 300-baud modem, LIN
Bus master and slave, fan controller, and magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, com-
pile, link, and build.
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Assembler. The macro assembler allows the assembly code
to be merged seamlessly with C code. The link libraries auto-
matically use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available
that supports PSoC family devices. Even if you have never
worked in the C language before, the product quickly allows you
to create complete C programs for the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read the
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
PSoC Express Software
PSoC Express is the first visual embedded system design tool
that allows a user to create an entire PSoC Project, generate a
schematic, BOM, and data sheet without writing a single line of
code. System designers are finally free from the low-level
implementation details of "micro-coding" to work directly with
application objects such as LEDs, switches, sensors, and fans.
Because the details of the actual firmware are left to the PSoC
Express firmware generation engine, and hidden from the user,
not only are design cycles reduced from weeks and months to a
few hours, but the generated, fully-tested ‘C' code is completely
standardized, considerably increasing overall design quality
and maintainability. Go to http://www.cypress.com/psocexpress
for free downloads and more information.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is avail-
able for development support. This hardware has the capability
to program single devices.
The emulator consists of a base unit that connects to the PC by
way of the parallel or USB port. The base unit is universal and
will operate with all PSoC devices. Emulation pods for each
device family are available separately. The emulation pod takes
the place of the PSoC device in the target board and performs
full speed (24 MHz) operation
May 24, 2005
Document No. 001-00353 Rev. **
5
5 Page 
CG64xxAM Preliminary Data Sheet
Register Map Bank 0 Table: User Space
2. Register Reference
PRT0DR
00 RW
40
PRT0IE
01 RW
41
PRT0GS
02 RW
42
PRT0DM2
03 RW
43
PRT1DR
04 RW
44
PRT1IE
05 RW
45
PRT1GS
06 RW
46
PRT1DM2
07 RW
47
08 48
09 49
0A 4A
0B 4B
0C 4C
0D 4D
0E 4E
0F 4F
10 50
11 51
12 52
13 53
14 54
15 55
16 56
17 57
18 58
19 59
1A 5A
1B 5B
1C 5C
1D 5D
1E 5E
1F 5F
DBB00DR0 20 #
AMX_IN
60 RW
DBB00DR1 21 W
61
DBB00DR2 22 RW PWM_CR
62 RW
DBB00CR0 23 #
63
DBB01DR0 24 #
CMP_CR0 64 #
DBB01DR1 25 W
65
www.DDDBBaBBta00S11DChRRee20t4U.22c67om
RW
#
CMP_CR1
66
67
RW
DCB02DR0 28 #
ADC0_CR 68 #
DCB02DR1 29 W ADC1_CR 69 #
DCB02DR2 2A RW
6A
DCB02CR0 2B #
6B
DCB03DR0 2C #
TMP_DR0 6C RW
DCB03DR1 2D W TMP_DR1 6D RW
DCB03DR2 2E RW TMP_DR2 6E RW
DCB03CR0 2F #
TMP_DR3 6F RW
30 70
31 71
32 ACE00CR1 72 RW
33 ACE00CR2 73 RW
34 74
35 75
36 ACE01CR1 76 RW
37 ACE01CR2 77 RW
38 78
39 79
3A 7A
3B 7B
3C 7C
3D 7D
3E 7E
3F 7F
Blank fields are Reserved and should not be accessed.
ASE10CR0 80 RW
81
82
83
ASE11CR0 84 RW
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0 RW
RDI0SYN
B1 RW
RDI0IS
B2 RW
RDI0LT0
B3 RW
RDI0LT1
B4 RW
RDI0RO0
B5 RW
RDI0RO1
B6 RW
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR3
INT_MSK3
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_CR0
DEC_CR1
CPU_F
CPU_SCR1
CPU_SCR0
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RC
W
RW
RW
RL
#
#
May 24, 2005
Document No. 001-00353 Rev. **
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet CG6457AM.PDF ] | |
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