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ADF9010 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF9010
Beschreibung 900 MHz ISM Band Analog RF Front End
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
ADF9010 Datasheet, Funktion
FEATURES
840 MHz to 960 MHz ISM bands
Rx baseband analog low-pass filtering and PGA
Integrated RF Tx upconverter
Integrated integer-N PLL and VCO
Integrated Tx PA preamplifier
Differential fully balanced architectures
3.3 V supply
Low power mode: <1 mA power-down current
Programmable Rx LPF cutoff
330 kHz, 880 kHz, 1.76 MHz, and bypass
Rx PGA gain settings: 3 dB to 24 dB in 3 dB steps
Low noise BiCMOS technology
48-lead, 7 mm × 7 mm LFCSP
APPLICATIONS
900 MHz RFID readers
Unlicensed band 900 MHz applications
GENERAL DESCRIPTION
The ADF9010 is a fully integrated RF Tx modulator and Rx
analog baseband front end that operates in the frequency
www.DaratanSgheeferot4mU.8c4om0 MHz to 960 MHz. The receive path consists
of a fully differential I/Q baseband PGA, low-pass filter, and
general signal conditioning before connecting to an Rx ADC
for baseband conversion. The Rx LPF gain ranges from 3 dB
to 24 dB, programmable in 3 dB steps. The Rx LPF features
four programmable modes with cutoff frequencies of 330 kHz,
880 kHz, and 1.76 MHz, or the filter can be bypassed if necessary.
900 MHz ISM Band
Analog RF Front End
ADF9010
RxINIP
RxININ
RxCM
RxINQP
RxINQN
MUXOUT
RSET
CP
VTUNE
LOOUTP
LOOUTN
TxOUTP
TxOUTN
FUNCTIONAL BLOCK DIAGRAM
RXVDD AVDD
VP DVDD
CE
VCM ADF9010
VCM
DC OFFSET
CORRECTION
RxBBIP
RxBBIN
OVF
DC OFFSET
CORRECTION
CHARGE
PUMP
PHASE
FREQUENCY
DETECTOR
R
COUNTER
B
COUNTER
A
COUNTER
÷4
QUADRATURE
PHASE SPLITTER
24-BIT
INPUT SHIFT
REGISTER
PLL
N COUNTER
N = BP + A
PRESCALER
P/P + 1
DGND
AGND
Figure 1.
RxBBQP
RxBBQN
SCLK
SDATA
SLE
REFIN
CEXT1
CEXT2
CEXT3
CEXT4
CT
TxBBIP
TxBBIN
TxBBQP
TxBBQN
The transmit path consists of a fully integrated differential Tx
direct I/Q upconverter with a high linearity PA driver amplifier.
It converts a baseband I/Q signal to an RF carrier-based signal
between 840 MHz and 960 MHz. The highly linear transmit
signal path ensures low output distortion.
Complete local oscillator (LO) signal generation is integrated
on chip, including the integer-N synthesizer and VCO, which
generate the required I and Q signals for transmit I/Q upconver-
sion. The LO signal is also available at the output to drive an
external RF demodulator. Control of all the on-chip registers
is via a simple 3-wire serial interface. The device operates with a
power supply ranging from 3.15 V to 3.45 V and can be powered
down when not in use.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.






ADF9010 Datasheet, Funktion
ADF9010
WRITE TIMING CHARACTERISTICS
AVDD = DVDD = 3.3 V ± 5%; AGND = DGND = GND = 0 V; TA = 25°C, guaranteed by design, but not production tested.
Table 4.
Parameter
t1
t2
t3
t4
t5
t6
Limit at tMIN to tMAX (B Version)
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
SDATA to SCLK setup time
SDATA to SCLK hold time
SCLK high duration
SCLK low duration
SCLK to SLE setup time
SLE pulse width
SCLCK
SDATA DB23 (MSB)
t1 t2
DB22
SLE
SLE
t3 t4
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t6
t5
Figure 2. Write Timing Diagram
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Rev. 0 | Page 6 of 28

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ADF9010 pdf, datenblatt
ADF9010
CIRCUIT DESCRIPTION
Rx SECTION
PGA
SETTING
OVF
RxINIP
RxININ
RxBBIP
RxBBIN
DC OFFSET
CORRECTION
Figure 12. Rx Filter
The Rx section of the ADF9010 features programmable base-
band low-pass filters. These are used to amplify the desired Rx
signal from the demodulator while removing the unwanted
portion to ensure no antialiasing occurs in the Rx ADC.
These filters have a programmable gain stage, allowing gain to
be selected from 3 dB to 24 dB in steps of 3 dB. The bandwidth
of these filters is also programmable, allowing 3 dB cutoff fre-
quencies of 330 kHz, 880 kHz, and 1.76 MHz, along with a
bypass mode. The filters utilize a fourth-order Bessel transfer
function (see the Specifications section for more information).
If desired, the filter stage can be bypassed.
Additionally, a rising edge on the OVF pin reduces the gain of
the Rx amplifiers by 6 dB. This is to correct a potential overflow
of the input to the ADC.
Updating the Rx calibration latch with the calibration bit
enabled calibrates the filter to remove any dc offset. The
3 dB cutoff frequency (fC) of the filters is calibrated also.
LO SECTION
wwLwO.DRaetfaeSrheenect4eUI.ncpomut Section
The LO input stage is shown in Figure 13. SW1 and SW2
are normally closed switches; SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
POWER-DOWN
CONTROL
NC 100k
REFIN NC
SW2
SW1
SW3
NO
TO R COUNTER
BUFFER
Figure 13. Reference Input Stage
R COUNTER
The 14-bit R counter allows the input clock frequency to be
divided down to produce the input clock to the phase frequency
detector (PFD). Division ratios from 1 to 8191 are allowed.
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide range of division ratios in the PLL
feedback counter. The counters are specified to work when
the prescaler output is 300 MHz or less.
Pulse Swallow Function
The A and B counters, in conjunction with the dual-modulus
prescaler (see Figure 14), make it possible to generate large
divider ratios. The equation for N is as follows:
N = BP + A
where:
N is the overall divider ratio of the signal from the external
RF input.
P is the preset modulus of the dual-modulus prescaler.
B is the preset divide ratio of the binary 13-bit counter (3 to 8191).
A is the preset divide ratio of the binary 5-bit swallow counter
(0 to 31).
N = BP + A
FROM RF
INPUT STAGE
PRESCALER
P/P + 1
MODULUS
CONTROL
13-BIT B
COUNTER
LOAD
LOAD
6-BIT A
COUNTER
TO PFD
N DIVIDER
Figure 14. A and B Counters
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it down
to a manageable frequency for the A and B CMOS counters.
The prescaler is programmable. The prescaler can be set in
software to 8/9, 16/17, or 32/33. For the ADF9010, however,
the 16/17 and 32/33 settings should be used. It is based on a
synchronous 4/5 core. A minimum divide ratio is possible for
fully contiguous output frequencies. This minimum is deter-
mined by P, the prescaler value, and is given by (P2 − P).
Rev. 0 | Page 12 of 28

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