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PDF R2J20653ANP Data sheet ( Hoja de datos )
| Número de pieza | R2J20653ANP | |
| Descripción | Integrated Driver | |
| Fabricantes | Renesas Technology | |
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Preliminary
R2J20653ANP
Integrated Driver – MOS FET (DrMOS)
REJ03G1849-0100
Rev.1.00
Dec 07, 2009
Description
The R2J20653ANP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver
in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this
device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating
the need for an external SBD for this purpose.
Features
• Compliant with Intel 6 × 6 DrMOS specification
• Built-in power MOS FET suitable for Notebook, Desktop, Server application
• Low-side MOS FET with built-in SBD for lower loss and reduced ringing
• Built-in driver circuit which matches the power MOS FET
• Built-in tri-state input function which can support a number of PWM controllers
• High-frequency operation (above 1 MHz) possible
• VIN operating-voltage range: 27 V max
• Large average output current (Max. 35 A)
• Achieve low power dissipation
• Controllable driver: Remote on/off
• Low-side MOS FET disabled function for DCM operation
• Double thermal protection: Thermal warning & Thermal shutdown
• Built-in bootstrapping switch
• Small package: QFN40 (6 mm × 6 mm × 0.95 mm)
• Terminal Pb-free/Halogen-free
Outline
www.DataSheet4U.com
THWN
DISBL#
LSDBL#
PWM
VCIN BOOT
Integrated Driver-MOS FET (DrMOS)
QFN40 package 6 mm × 6 mm
GH VIN
1
40
Driver
Pad
10
High-side
MOS Pad
11
MOS FET Driver
VSWH
Low-side MOS Pad
CGND VDRV
GL PGND
31
30
(Bottom view)
20
21
REJ03G1849-0100 Rev.1.00 Dec 07, 2009
Page 1 of 12
1 page  
R2J20653ANP
Preliminary
Electrical Characteristics
(Ta = 25°C, VCIN = 5 V, VDRV = 5 V, VSWH = 0 V, unless otherwise specified)
Item
Symbol
Min Typ Max Units
Test Conditions
Supply
VCIN start threshold
VCIN shutdown threshold
UVLO hysteresis
VCIN operating current
VH
VL
dUVL
ICIN
4.1 4.3
4.5
V
3.6 3.8
4.0
V
— 0.5 —
V VH – VL
— 33 — mA fPWM = 1 MHz,
Ton_pwm = 120 ns
VCIN disable current
ICIN-DISBL
——
2 mA DISBL# = 0 V, PWM = 0 V,
LSDBL# = Open
PWM
input
PWM rising threshold
PWM falling threshold
VH-PWM
VL-PWM
3.0 3.4
0.9 1.2
PWM input resistance
RIN-PWM
10 20
Tri-state shutdown window
Shutdown hold-off time
VIN-SD
tHOLD-OFF *1
VL-PWM
—
—
100
DISBL#
input
Disable threshold
Enable threshold
VDISBL
VENBL
0.9 1.2
1.9 2.4
Input current
THDN on resistance
IDISBL
RTHDN *1
— 2.0
0.2 0.5
LSDBL#
input
Low-side activation threshold
Low-side disable threshold
VLSDBLH
VLSDBLL
1.9 2.4
0.9 1.2
Thermal
warning
Input current
Warning temperature
Temperature hysteresis
THWN on resistance
ILSDBL
TTHWN *1
THYS *1
RTHWN *1
–56 –27
95 115
— 15
0.2 0.5
Thermal
THWN leakage current
Shutdown temperature
ILEAK
Tstdn *1
— 0.001
130 150
shutdown Temperature hysteresis
TDHYS *1
— 15
Note: 1. Reference values for design. Not 100% tested in production.
3.8
1.5
40
VH-PWM
—
1.5
2.9
5.0
1.0
2.9
1.5
–14
135
—
1.0
1.0
—
—
V
V
kΩ PWM = 1 V
V
ns
V
V
μA DISBL# = 1 V
kΩ THDN = 0.2 V
V
V
μA LSDBL# = 1 V
°C Driver IC temperature
°C
kΩ THWN = 0.2 V
μA THWN = 5 V
°C Driver IC temperature
°C
www.DataSheet4U.com
REJ03G1849-0100 Rev.1.00 Dec 07, 2009
Page 5 of 12
5 Page 
R2J20653ANP
Preliminary
THDN is an internal thermal shutdown signal when driver IC becomes over 150°C.
This function makes high-side MOS FET and low-side MOS FET turn off for the device protection from abnormal high
temperature situation and at the same time DISBL# pin is pulled low internally to give notice to the system controller.
Figure 5 shows the example of two types of DISBL# connection with the system controller signal.
Driver IC Temp.
< 150°C
(< 135°C on cancellation)
> 150°C
Driver Chip Status
Enable (GL, GH = "Active")
Shutdown (GL, GH = "L")
5V
10 k
DISBL#
To shutdown signal
2 μA
To Internal
Logic
Thermal
Shutdown
Detection
10 k DISBL#
ON/OFF signal
2 μA
To Internal
Logic
Thermal
Shutdown
Detection
Figure 5.1 THDN Signal to the System Controller Figure 5.2 ON/OFF Signal from the System Controller
MOS FETs
The MOS FETs incorporated in R2J20653ANP are highly suitable for synchronous-rectification buck conversion. For
the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the
low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin.
www.DataSheet4U.com
REJ03G1849-0100 Rev.1.00 Dec 07, 2009
Page 11 of 12
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