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R2J20604NP Schematic ( PDF Datasheet ) - Renesas Technology

Teilenummer R2J20604NP
Beschreibung Integrated Driver
Hersteller Renesas Technology
Logo Renesas Technology Logo 




Gesamt 15 Seiten
R2J20604NP Datasheet, Funktion
R2J20604NP
Integrated Driver – MOS FET (DrMOS)
REJ03G1605-0200
Rev.2.00
Jun 30, 2008
Description
The R2J20604NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in
a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this
device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap Schottky barrier
diode (SBD), eliminating the need for an external SBD for this purpose.
Integrating a driver and both high-side and low-side power MOS FETs, the new device is also compliant with the
package standard “Integrated Driver – MOS FET (DrMOS)” proposed by Intel Corporation.
Features
Built-in power MOS FET suitable for applications with 12 V input and low output voltage
Built-in driver circuit which matches the power MOS FET
Built-in tri-state input function which can support a number of PWM controllers
Capable of 3.3 V PWM signal
VIN operating-voltage range: 16 V max
High-frequency operation (above 1 MHz) possible
Large average output current (Max. 40 A)
Achieve low power dissipation (About 4.4 W at 1 MHz, 25 A)
Controllable driver: Remote on/off
Built-in Schottky diode for bootstrapping
Low-side drive voltage can be independently set
Small package: QFN56 (8 mm × 8 mm × 0.95 mm)
Terminal Pb-free
Outline
www.DataSheet4U.com
VCIN BOOT
GH VIN
1 14
Reg5V
56 15
Driver
Tab
High-side MOS
Tab
DISBL#
PWM
MOS FET Driver
VSWH
43
Low-side MOS Tab
28
CGND VLDRV
GL PGND
42 29
(Bottom view)
QFN56 package 8 mm × 8 mm
REJ03G1605-0200 Rev.2.00 Jun 30, 2008
Page 1 of 14






R2J20604NP Datasheet, Funktion
R2J20604NP
Typical Application
+12 V
+5 V to 12 V
+12 V
PWM1
PWM PWM2
control
circuit PWM3
PWM4
www.DataSheet4U.com
VCIN VLDRV BOOT
DISBL#
VIN
Reg5V
VSWH
R2J20604NP
PWM
PGND
CGND GH GL
VCIN VLDRV BOOT
DISBL#
VIN
Reg5V
VSWH
R2J20604NP
PWM
PGND
CGND GH GL
VCIN VLDRV BOOT
DISBL#
VIN
Reg5V
VSWH
R2J20604NP
PWM
PGND
CGND GH GL
VCIN VLDRV BOOT
DISBL#
VIN
Reg5V
VSWH
R2J20604NP
PWM
PGND
CGND GH GL
+1.3 V
Signal Power
GND GND
REJ03G1605-0200 Rev.2.00 Jun 30, 2008
Page 6 of 14

6 Page









R2J20604NP pdf, datenblatt
R2J20604NP
PCB Layout Example
Figure 2 shows an example of a PCB layout for the R2J20604NP in application. The several ceramic capacitors (e.g. 10
µF) close to VIN and PGND can be expected to decrease switching noise and improve efficiency. In that case, all
sections of the GND pattern must be connected with other PCB layers via low impedances. Moreover, the wide VSWH
pattern can be expected to have the effect of dissipating heat from the low-side MOS FET.
When R2J20604NP is mounted on small circuit boards, such as those for point-of-load (POL) applications, heating of
the device can be alleviated by adding thermal via-holes under the VIN and VSWH pads.
10 µF
10 µF
Vin
10 µF
GND
VSWH
To inductor
10 µF
GND
BOOT
1 µF
VCIN
1 µF
VLDRV
PWM
GND
DISBL#
1 µF
0.1 µF
GND
To
BOOT
www.DataSheet4U.com
Via hole
Figure 2 R2J20604NP PCB Layout Example (Top View)
REJ03G1605-0200 Rev.2.00 Jun 30, 2008
Page 12 of 14

12 Page





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