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PDF A3904 Data sheet ( Hoja de datos )
| Número de pieza | A3904 | |
| Descripción | Low Voltage Voice Coil Motor Driver | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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A3904
Low Voltage Voice Coil Motor Driver
Features and Benefits
▪ Fixed I2C logic thresholds
▪ 8-bit D-to-A converter
▪ 500 μA resolution
▪ Low voltage I2C serial interface
▪ Low current-draw sleep mode
▪ 2.4 to 5.5 V operation
▪ 2 mm × 1.5 mm, 0.38 mm nominal overall height DFN
▪ 1.1 mm × 0.7 mm, 0.5 mm maximum overall height WLCSP
▪ 1.1 mm × 0.7 mm, 0.33 mm nominal overall height bare die
Packages:
1.5 mm × 2 mm DFN
(EW package)
1.1 mm × 0.7 mm WLCSP
(CG package)
Not to scale
Bare die
(CW package)
Description
The A3904 is a voice coil motor (VCM) driver, with an
I2C-compatible serial interface. Designed for camera autofocus
and zoom applications, this high accuracy digital IC is provided
in small packages ideal for portable devices. Its operating
voltage range is 2.4 to 5.5 V, and its maximum output current
is 127 mA.
Output current is programmed via the I2C interface, in 500 uA
increments, with clock rates up to 400 kHz. I2C inputs set the
internal D-to-A converter output voltage that is the reference
for linear current control via a MOSFET output sink transistor.
To conserve battery power, a logic low signal on the SLEEPZ
input disables the output MOSFET and reduces the supply
current to <0.5 μA.
A3904 internal protection features include thermal shutdown
and undervoltage lockout. Logic input levels are independent
of the supply voltage. The operating temperature range is
–40°C to 85°C.
The A3904 is available at three packaging levels: bare die on
wafer (suffix CW); bumped wafer level chip scale package
(WLCSP) (suffix CG); and complete thin profile (0.38 mm
nominal overall height) DFN package, with NiAuPd leadframe
plating and an exposed tab for enhanced thermal dissipation
(suffix EW).
www.DataSheet4U.com
Functional Block Diagram
1.8 V
2.4 to 5.5 V
1.8 kΩ
1.8 kΩ
I2C
Master
I2C
Slave
VDD
SDA
SCL
SLEEPZ
Bandgap
Ref
I2C Serial
Interface
8 Bit DAC
EW only
PAD
IOUT
2.4 Ω
GND
3904-DS, Rev. 2
1 page  
A3904
Low Voltage Voice Coil Motor Driver
Functional Description
The A3904 output current is controlled by programming the D-to-
A converter value via the I2C serial port. The target output current
can be calculated by:
IOUT = DAC × 500 μA ,
where DAC = 1 to 255. Code = 0 is a disable state for the output
sink drive. The DAC will be set to code = 0 upon power-up or a
fault condition on VDD.
SLEEPZ A logic low input disables all of the internal circuitry
and prevents the IC from draining battery power.
Output Range The voltage on the IOUT pin should be greater
than 500 mV to guarantee the accuracy and linearity of the pro-
grammed current. The output voltage is a function of the battery
voltage, motor resistance, and the programmed load current.
Clamp Diode When the output is turned off, the load induc-
tance causes the output voltage to rise. A clamp diode, from
IOUT to VDD, is integrated in the IC to ensure that the output
voltage remains at a safe level.
I2C Interface This is a serial interface that uses two bus lines,
SCL and SDA, to access the internal Control registers. Data is
wwewxc.DhaatnagSehdeebte4tUw.ceoemn a microcontroller (master) and the A3904
(slave). The clock input to SCL is generated by the master, while
the SDA line functions as either an input or an open drain output,
depending on the direction of the data. The I2C input thresholds
do not depend on the VDD voltage of the A3904. The levels are
fixed at approximately 1 V. The fixed levels allow the SDA and
SCL lines to be pulled-up to a different logic level than the VDD
supply of the 3904.
Timing Considerations The control sequence of the com-
munication through the I2C interface is composed of several steps
in the following sequence:
1. Start Condition. Defined by a negative edge on the SDA
line, while SCL is high.
2. Address Cycle. 7 bits of address, plus 1 bit to indicate
write (0) or read (1), and an acknowledge bit. The ad-
dress setting is 0x18, 0x1A, 0x1C or 0x1E.
3. Data Cycles. Write 8 bits of data that address the internal
Control register, followed by an acknowledge bit.
4. Stop Condition. Defined by a positive edge on the SDA
line, while SCL is high.
Except to indicate a Start or Stop condition, SDA must be stable
while the clock is high. SDA can only be changed while SCL is
low. It is possible for the Start or Stop condition to occur at any
time during a data transfer. The A3904 always responds by reset-
ting the data transfer sequence.
The Read/Write bit is set low to indicate a write cycle. Multiple
writes are allowed before issuing a Stop condition. There are no
readback functions incorporated into the A3904.
The master monitors for an acknowledge pulse to determine if the
slave device is responding to the address byte sent to the A3904.
When the A3904 decodes the 7-bit address field as a valid
address, it responds by pulling SDA low during the ninth clock
cycle.
During a data write from the master, the A3904 pulls SDA low
during the clock cycle that follows the data byte, in order to indi-
cate that the data has been successfully received.
After sending either an address byte or a data byte, the master
device must release the SDA line before the ninth clock cycle, in
order to allow this handshaking to occur.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet A3904.PDF ] | |
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