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AD5512A Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5512A
Beschreibung (AD5512A - AD5542A) 16-/12-Bit NanoDAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
AD5512A Datasheet, Funktion
2.7 V to 5.5 V, Serial-Input, Voltage-Output,
16-/12-Bit nanoDACs in LFCSP
Preliminary Technical Data
AD5541A/AD5542A/AD5512A
FEATURES
Low power, 1 LSB INL nanoDACs
AD5541A: 16 bits
AD5542A: 16 bits
AD5512A: 12 bits
2.7 V to 5.5 V single-supply operation
Low glitch: 0.5 nV-s
Unbuffered voltage output capable of driving 60 kΩ loads
directly
VLOGIC pin provides 1.8 V digital interface capability
Hardware CLR and LDAC functions
50 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible interface
standards
Power-on reset clears DAC output to zeroscale and midscale
Schmitt trigger inputs
Available in 3 mm × 3 mm 16-LFCSP, 10-LFCSP, and 8-LFCSP
Also available in10-MSOP and 16-TSSOP
APPLICATIONS
Automatic test equipment
Precision Source-measure Instruments
Data Acquisition Systems
Medical Instrumentation
Aerospace Instrumentation
Communications Infrastructure equipment
Industrial Control
GENERAL DESCRIPTION
The AD5541A/AD5542A/AD5512A1 are single, 16-/16-/12-bit,
www.DasetariSahleinept4uUt,.cuonmbuffered voltage output digital-to-analog conver-
ters (DACs) that operate from a single 2.7 V to 5.5 V supply.
The AD5541A/AD5542A/AD5512A utilize a versatile 3-wire
interface that is compatible with a 50 MHz SPI, QSPI™,
MICROWIRE™, and DSP interface standards.
These DACs provide 16-/12-bit performance without any adjust-
ments. The DAC output is unbuffered, which reduces power
consumption and offset errors contributed to by an output buffer.
The AD5542A/AD5512A can be operated in bipolar mode, which
generates a ±VREF output swing. The AD5542A/AD5512A also
includes Kelvin sense connections for the reference and analog
ground pins to reduce layout sensitivity.
The AD5541A is available in 10-lead 3 mm × 3 mm LFCSP and
10-lead MSSOP. The AD5541A-1 is available in 8-lead 3 mm ×
3 mm LFCSP. The AD5542A/AD5512A are available in 16-lead
3 mm × 3 mm LFCSP and the AD5542A is also available in
16-lead TSSOP. The AD5542A-1 is available in 10-lead LFCSP.
The AD5541A and AD5542A are specified over a temperature
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
range of −40°C to 105°C.
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. AD5541A
Figure 2. AD5541A-1
Figure 3. AD5542A
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.






AD5512A Datasheet, Funktion
AD5541A/AD5542A/AD5512A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to AGND
Digital Input Voltage to DGND
VOUT to AGND
AGND, AGNDF, AGNDS to DGND
Input Current to Any Pin Except Supplies
Operating Temperature Range
Industrial (A, B, C Versions)
Commercial (J, L Versions)
Storage Temperature Range
Maximum Junction Temperature (TJ max)
Package Power Dissipation
Thermal Impedance, θJA
SOIC (R-8)
SOIC (R-14)
Lead Temperature, Soldering
Peak Temperature1
Rating
−0.3 V to +6 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +0.3 V
±10 mA
−40°C to +85°C
0°C to 70°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
149.5°C/W
104.5°C/W
260°C
1 As per JEDEC Standard 20.
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
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Rev. PrA | Page 6 of 24

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AD5512A pdf, datenblatt
AD5541A/AD5542A/AD5512A
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or INL is a measure of the
maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function. A typical
INL vs. code plot is shown in Figure 14.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures mono-
tonicity. A typical DNL vs. code plot is shown in Figure 17.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range.
It is the deviation in slope of the DAC transfer characteristic
from ideal.
Gain Error Temperature Coefficient
Gain error temperature coefficient is a measure of the change
in gain error with changes in temperature. It is expressed in
ppm/°C.
Zero Code Error
Zero code error is a measure of the output error when zero code
is loaded to the DAC register.
Zero Code Temperature Coefficient
This is a measure of the change in zero code error with a change
in temperature. It is expressed in mV/°C.
Preliminary Technical Data
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by
1 LSB at the major carry transition. A digital-to-analog glitch
impulse plot is shown in Figure 27.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but it is measured when the DAC output is not updated.
CS is held high while the CLK and DIN signals are toggled. It
is specified in nV-sec and is measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice
versa. A typical digital feedthrough plot is shown in Figure 26.
Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the power supply voltage. Power-supply rejection ratio is
quoted in terms of percent change in output per percent change
in VDD for full-scale output of the DAC. VDD is varied by ±10%.
Reference Feedthrough
Reference feedthrough is a measure of the feedthrough from the
VREF input to the DAC output when the DAC is loaded with all
0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough
is expressed in mV p-p.
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