Datenblatt-pdf.com


PCA9702 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCA9702
Beschreibung (PCA9701 / PCA9702) 18 V tolerant SPI 16-bit/8-bit GPI
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 28 Seiten
PCA9702 Datasheet, Funktion
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
Rev. 03 — 3 December 2008
Product data sheet
1. General description
The PCA9701/PCA9702 are low power 18 V tolerant SPI General Purpose Input (GPI)
shift register designed to monitor the status of switch inputs. It generates an interrupt
when one or more of the switch inputs change state. The input level is recognized as a
HIGH when it is greater than 0.7 × VDD and as a LOW when it is less than 0.4 × VDD
(minimum threshold of 2 V at 5 V node). The PCA9701 can monitor up to 16 switch inputs
and the PCA9702 can monitor up to 8 switch inputs.
The falling edge of the CS pin samples the input port status and clears the interrupt. When
CS is LOW, the rising edge of the SCLK loads the shift register and shifts the value out of
the shift register. The serial input is sampled on the falling edge of SCLK.
Each of the input ports has a 18 V breakdown ESD protection circuit. When used with a
series resistor (minimum 100 k), the input can connect to a 12 V battery and support
double battery, reverse battery, 27 V jump start and 40 V load dump conditions in
automotive applications. Higher voltages can be tolerated on the inputs depending on the
series resistor used to limit the input current.
With both the high breakdown voltage and high ESD, these devices are useful for both
automotive (AEC-Q100 qualification available) and mobile applications.
The PCA9703/PCA9704 are new pin compatible devices for the PCA9701/PCA9702
which have an interrupt masking feature allowing selected inputs to not generate
interrupts and provides higher ground offset of 0.55 × VDD (minimum of 2.5 V at 5 V node)
with minimum hysteresis of 0.05 × VDD (minimum of 225 mV at 5 V node).
www.D2a.taSheFeet4Ua.ctoumres
I 16 general purpose input ports (PCA9701) or 8 general purpose input ports
(PCA9702)
I 18 V tolerant input ports with 100 kexternal series resistor
I Input LOW threshold 0.4 × VDD with minimum of 2 V at VDD = 4.5 V
I Open-drain interrupt output
I Interrupt enable pin (INT_EN) disables interrupt output
I VDD range: 2.5 V to 5.5 V
I IDD is very low 2.5 µA maximum
I SPI serial interface with speeds up to 5 MHz
I AEC-Q100 qualification available
I ESD protection exceeds 8 kV HBM per JESD22-A114, 350 V MM per AEC-Q100, and
1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA






PCA9702 Datasheet, Funktion
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
7. Functional description
PCA9701 is a 16-bit General Purpose Input (GPI) with an open-drain interrupt output
designed to monitor switch status. By putting an external 100 kseries resistor at the
input port, the device allows the input to tolerate momentary double 12 V battery, reverse
battery, 27 V jump start or 40 V load dump conditions. The interrupt output is asserted
when an input port status changes. The open-drain interrupt output is enabled when
INT_EN is HIGH and disabled when INT_EN is LOW. The input port status is accessed
via the 4-wire SPI interface. The PCA9702 is the 8-bit version of the PCA9701.
Multiple PCA9701 or PCA9702 devices can be serially connected for monitoring a large
number of switches by connecting the SDOUT of one device to the SDIN of the next
device. SCLK and CS must be common among all devices and interrupt outputs may be
tied together. No external logic is necessary because all the devices’ interrupt outputs are
open-drain that function as ‘wired-AND’ and can simply be connected together to a single
pull-up resistor.
7.1 SPI bus operation
The PCA9701 or PCA9702 interfaces with the controller via the 4-wire SPI bus that is
comprised of the following signals: chip select (CS), serial clock (SCLK), serial data in
(SDIN), and serial data out (SDOUT). To access the device, the controller asserts CS
LOW, then sends SCLK and SDIN. When reading/writing is complete, the controller
de-asserts CS. See Figure 6 for register access timing.
7.1.1 CS - chip select
The CS pin is the device chip select and is an active LOW input. The falling edge of CS
captures the input port status in the input status register. If the interrupt output is asserted,
the falling edge of CS will clear the interrupt. When CS is LOW, the SPI interface is active.
When CS is HIGH, the SPI interface is disabled.
www.DataSheet4U.com 7.1.2 SCLK - serial clock input
SCLK is the serial clock input to the device. It should be LOW and remain LOW during the
falling and rising edge of CS. When CS is LOW, the first rising edge of SCLK parallel loads
the shift register from the input. The subsequent rising edges on SCLK serially shifts data
out from the shift register. The falling edge of SCLK samples the data on SDIN.
7.1.3 SDIN - serial data input
SDIN is the serial data input port. The data is sampled into the shift register on the falling
edge of SCLK. SDIN is only active when CS is LOW. This input has a 20 µA pull-down
current source.
7.1.4 SDOUT - serial data output
SDOUT is the serial data output signal. SDOUT is high-impedance when CS is HIGH and
switches to low-impedance after CS goes LOW. When CS is LOW, after the first rising
edge of SCLK the most significant bit in the shift register is presented on SDOUT.
Subsequent rising edges of SCLK shift the remaining data from the shift register onto
SDOUT.
PCA9701_PCA9702_3
Product data sheet
Rev. 03 — 3 December 2008
© NXP B.V. 2008. All rights reserved.
6 of 28

6 Page









PCA9702 pdf, datenblatt
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
8.2.1.2 UJA106x with PCA9701, sleep
alternate
PVR100AD-B5V0
alternate
PMEM4010ND
V3
IN0 VDD INT_EN
IN1 INT
PCA9701
IN15
CS
SDIN
SDOUT
SCLK
VSS
alternate
PDTC144TU
UJA106x
WAKE
RSTN
V1 GND
VCC
CSN
MOSI
µC
MISO
SCLK
GND
002aae017
Fig 10. UJA106x with PCA9701 with unsupplied µC (sleep)
Very low quiescent system current (50 µA) due to disabled µC and cyclically biasing
of switches
Wake-up upon change of switches or upon bus traffic (CAN and LIN)
PCA970x supplied out of cyclically biased transistor regulator
www.DataSheet4U.com
PCA9701_PCA9702_3
Product data sheet
Rev. 03 — 3 December 2008
© NXP B.V. 2008. All rights reserved.
12 of 28

12 Page





SeitenGesamt 28 Seiten
PDF Download[ PCA9702 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
PCA9701(PCA9701 / PCA9702) 18 V tolerant SPI 16-bit/8-bit GPINXP Semiconductors
NXP Semiconductors
PCA9702(PCA9701 / PCA9702) 18 V tolerant SPI 16-bit/8-bit GPINXP Semiconductors
NXP Semiconductors
PCA970318 V Tolerant SPI 16-bit GPI With Maskable INTNXP Semiconductors
NXP Semiconductors

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche