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PDF ADA4424-6 Data sheet ( Hoja de datos )
| Número de pieza | ADA4424-6 | |
| Descripción | 6-Channel SD/ED/HD Video Filter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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6-Channel SD/ED/HD Video Filter with
Charge Pump
ADA4424-6
FEATURES
3 SD channels; 18 MHz typical 1 dB bandwidth (BW)
3 ED/HD channels; 25 MHz/34 MHz typical 1 dB BW
Fixed gain of 6.2 dB (2.042 V/V)
On-board negative supply for output coupling without
capacitors
Minimal dc offset at the output pins
Internal summation of Y and C channels for CVBS output
Flexible input dc offset cancellation for luma channels
D-terminal (EIAJ RC-5237 D5) and S-terminal (S1/S2) support
Capable of driving 2 back-terminated 75 Ω video loads
simultaneously
Separate power-down pins for SD and ED/HD sections
38-lead TSSOP package
Sony Green Partner Environmental Quality Approval
Program compliant
APPLICATIONS
DVD players and recorders
Set-top boxes
Projectors
Personal video recorders
GENERAL DESCRIPTION
The ADA4424-6 is a high performance video reconstruction filter
www.DasptaeScihfieceatl4lyUd.ceosmigned for consumer applications. It consists of a
standard definition (SD) section with two fifth-order Butterworth
filters, and a high definition (HD) section with three fifth-order
filters. The SD section contains an internal Y/C summer for CVBS
output, whereas the HD section provides selectable corner
frequencies for either extended definition (ED) or HD signals.
The ADA4424-6 filter/buffer section operates from a single 3.3 V
supply. Full support for D-terminal (EIAJ RC-5237 D5) and S1/S2
signaling is provided, along with a dedicated 5 V supply pin.
Separate enable pins are provided for the SD and HD sections.
FUNCTIONAL BLOCK DIAGRAM
+3.3V
+5V
VDD3_SD
VDD3_HD VDD5
D1 L1 L1_OUT
D2
D3
D/S
TERMINAL
L2
L2_OUT
HD_ENB
CONTROL
L3
L3_OUT
S S1/S2
SD_ENB
S1/S2_OUT
Y_IN
C_IN
MODE0
MODE1
OFFSET_ENB
HY_IN
HPb_IN
HPr_IN
FC_SEL
SD_ENABLE
HD_ENABLE
×1
LPF
×2
×2
Y_OUT
CVBS_OUT
×1
LPF
×2
C_OUT
OFFSET
CANCELLATION
ADA4424-6
FC_SEL
×1
FC_SEL
×1
FC_SEL
×1
LPF
LPF
LPF
×2
×2
×2
SD_ENB HD_ENB
POWER
MANAGEMENT
CHARGE PUMP
HY_OUT
HPb_OUT
HPr_OUT
VSS_SD
VSS_HD
VDD3_CP C1a
C1b C2/CP_OUT
GND_CP
+3.3V C1
C2
Figure 1.
The luma channels (Y_IN, HY_IN) of the ADA4424-6 are
capable of detecting and cancelling dc input offsets of up to
1.1 V. Four distinct modes of detection/cancellation are
available.
The output drivers on the ADA4424-6 feature rail-to-rail outputs
with 6.2 dB gain. An on-board charge pump allows the outputs to
swing up to 1.4 V below ground, eliminating the need for large
coupling capacitors. Each output is capable of driving two 75 Ω
doubly terminated cables.
The ADA4424-6 is available in a 38-lead TSSOP and operates in
the extended industrial temperature range of −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
3.3 V Supply Voltage
5 V Supply Voltage
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
Rating
3.6 V
5.5 V
See Figure 2
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the device soldered to a high thermal
conductivity 4-layer (2s2p) circuit board, as described in
EIA/JESD 51-7.
Table 3.
Package Type
38-Lead TSSOP
θJA θJC Unit
67.6 14.0 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4424-6
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 150°C, which is the glass
www.DatrtaanSshietieotn4Ute.cmomperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the ADA4424-6. Exceeding a
junction temperature of 150°C for an extended time can result
in changes in the silicon devices, potentially causing failure.
ADA4424-6
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The power dissipated due to load drive
depends on the particular application. For each output, the
power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
power dissipated due to the loads is equal to the sum of the
power dissipations due to each individual load. RMS voltages
and currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θJA.
Figure 2 shows the maximum power dissipation in the package
vs. the ambient temperature for the 38-lead TSSOP (67.6°C/W)
on a JEDEC standard 4-layer board. θJA values are approximate.
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0 10 20 30 40 50 60 70 80 90 100
AMBIENT TEMPERATURE (°C)
Figure 2. Maximum Power Dissipation vs.
Ambient Temperature for a 4-Layer Board
ESD CAUTION
Rev. 0 | Page 5 of 16
5 Page 
Fixed Offset Cancellation Mode
In addition to the automatic mode, there are two levels of fixed
offset correction available. In high offset mode, fixed voltages of
1.0 V and 1.1 V are subtracted from the Y_IN and HY_IN inputs,
respectively. In low offset mode, a fixed voltage of 0.33 V is
subtracted from both Y_IN and HY_IN. The various modes of
offset cancellation are outlined in Table 6.
Table 6. Offset Cancellation Mode Selection
MODE1
(Pin 23)
MODE0
(Pin 16)
Output Offset Cancellation
Low (0)
Low (0)
Auto-cancel, sync-tip sampling mode.
Clamps the input referred SD sync tip
to −214 mV, and the input referred
ED/HD sync tip to −300 mV.
Low (0)
High (1)
Auto-cancel, back porch sampling
mode. Sets the output blanking level
to 0 V, independent of sync depth.
High (1) Low (0)
Fixed cancellation mode, high dc
offset.
Subtracts 1.0 V from the Y_IN signal;
subtracts 1.1 V from the HY_IN signal.
High (1) High (1) Fixed cancellation mode, low dc offset.
Subtracts 0.33 V from both the Y_IN
and HY_IN signals.
Offset Cancellation Disable
The offset cancellation function can be enabled or disabled via
the OFFSET_ENB pin, as described in Table 7.
Table 7. Offset Cancellation Enable/Disable
OFFSET_ENB
(Pin 17)
Offset Cancellation State
Low (0)
Offset cancellation disabled.
High (1)
Offset cancellation is enabled. Function is
www.DataSheet4U.com determined by the MODE1 and MODE0 pins
(see Table 6).
ADA4424-6
D-TERMINAL AND S-TERMINAL SUPPORT
Full D-terminal support (EIAJ RC-5237 D5) is provided for the
component channels (HY_OUT, HPb_OUT, HPr_OUT). Level
D1 through Level D5 are supported for vertical resolution, scan
type, and aspect ratio selection. Details are shown in Table 8,
Table 9, and Table 10.
S-terminal (also known as S_DC or S1/S2) support for S-video
aspect ratio selection is also provided, as described in Table 11.
The VDD5 pin (Pin 38) provides 5 V power for these outputs.
If D- or S-terminal support is not required, it is recommended
that Pin 2 to Pin 5 and Pin 34 to Pin 38 remain unconnected.
Table 8. D-Terminal Control for Vertical Resolution Selection
Input Logic Level
D1 (Pin 2)
Low (0)
Nominal Output (V)
L1_OUT (Pin 37)
RL = 100 kΩ
0.0
Vertical
Resolution
(No. of Lines)
480
High-Z (Open)
2.1
720
High (1)
4.5
1080
Table 9. D-Terminal Control for Scan Selection
Input Logic Level
D2 (Pin 3)
Low (0)
Nominal Output (V)
L2_OUT (Pin 36)
RL = 100 kΩ
0.0
Scan Type
Interlaced
High-Z (Open)
2.1
N/A
High (1)
4.5
Progressive
Table 10. D-Terminal Control for Aspect Ratio Selection
Input Logic Level
D3 (Pin 4)
Low (0)
Nominal Output (V)
L3_OUT (Pin 35)
RL = 100 kΩ
0.0
Aspect Ratio
4:3
High-Z (Open)
2.1
4:3 letterbox
High (1)
4.5
16:9
Table 11. S-Terminal Control for Aspect Ratio Selection
Input Logic Level
S (Pin 5)
Low (0)
Nominal Output (V)
S1/S2_OUT (Pin 34)
RL = 100 kΩ
0.0
Aspect Ratio
4:3
High-Z (Open)
2.1
4:3 letterbox
High (1)
4.5
16:9
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADA4424-6.PDF ] | |
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