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AD9115 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9115
Beschreibung 8-/10-/12-/14-Bit Low Power Digital-to-Analog Converters
Hersteller Analog Devices
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Gesamt 30 Seiten
AD9115 Datasheet, Funktion
Data Sheet
Dual Low Power, 8-/10-/12-/14-Bit
TxDAC Digital-to-Analog Converters
AD9114/AD9115/AD9116/AD9117
FEATURES
Power dissipation @ 3.3 V, 20 mA output
191 mW @ 10 MSPS
232 mW @ 125 MSPS
Sleep mode: <3 mW @ 3.3 V
Supply voltage: 1.8 V to 3.3 V
SFDR to Nyquist
86 dBc @ 1 MHz output
85 dBc @ 10 MHz output
AD9117 NSD @ 1 MHz output, 125 MSPS, 20 mA: −162 dBc/Hz
Differential current outputs: 2 mA to 20 mA
2 on-chip auxiliary DACs
CMOS inputs with single-port operation
Output common mode: adjustable 0 V to 1.2 V
Small footprint 40-lead LFCSP RoHS-compliant package
APPLICATIONS
Wireless infrastructures
Picocell, femtocell base stations
Medical instrumentation
Ultrasound transducer excitation
Portable instrumentation
Signal generators, arbitrary waveform generators
GENERAL DESCRIPTION
The AD9114/AD9115/AD9116/AD9117 are pin-compatible
dual, 8-/10-/12-/14-bit, low power digital-to-analog converters
(DACs) that provide a sample rate of 125 MSPS. These TxDAC®
converters are optimized for the transmit signal path of commu-
nication systems. All the devices share the same interface, package,
and pinout, providing an upward or downward component
selection path based on performance, resolution, and cost.
The AD9114/AD9115/AD9116/AD9117 offer exceptional ac and
dc performance and support update rates up to 125 MSPS.
The flexible power supply operating range of 1.8 V to 3.3 V and
low power dissipation of the AD9114/AD9115/AD9116/AD9117
make them well suited for portable and low power applications.
PRODUCT HIGHLIGHTS
1. Low Power. DACs operate on a single 1.8 V to 3.3 V supply;
total power consumption reduces to 225 mW at 100 MSPS.
Sleep and power-down modes are provided for low power
idle periods.
2. CMOS Clock Input. High speed, single-ended CMOS clock
input supports a 125 MSPS conversion rate.
3. Easy Interfacing to Other Components. Adjustable output
common mode from 0 V to 1.2 V allows for easy interfacing
to other components that accept common-mode levels
greater than 0 V.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2013 Analog Devices, Inc. All rights reserved.






AD9115 Datasheet, Funktion
AD9114/AD9115/AD9116/AD9117
Data Sheet
Parameter
AUXDAC OUTPUTS
Resolution
Full-Scale Output Current
(Current Sourcing Mode)
Voltage Output Mode
Output Compliance Range
(Sourcing 1 mA)
Output Compliance Range
(Sinking 1 mA)
Output Resistance in Current
Output Mode AVSS to 1 V
AUXDAC Monotonicity
Guaranteed
REFERENCE OUTPUT
Internal Reference Voltage
Output Resistance
REFERENCE INPUT
Voltage Compliance
AVDD = 3.3 V
AVDD = 1.8 V
Input Resistance External
Reference Mode
DAC MATCHING
Gain Matching
ANALOG SUPPLY VOLTAGES
AVDD
CVDD
DIGITAL SUPPLY VOLTAGES
DVDD
DVDDIO
POWER CONSUMPTION, AVDD =
DVDDIO = CVDD = 3.3 V
fDAC = 125 MSPS, IF = 12.5 MHz
IAVDD
IDVDD + IDVDDIO
ICVDD
Power-Down Mode with Clock
Power-Down Mode No Clock
Power Supply Rejection Ratio
POWER CONSUMPTION, AVDD =
DVDDIO = CVDD = 1.8 V
fDAC = 125 MSPS, IF = 12.5 MHz
IAVDD
IDVDD + IDVDDIO
ICVDD
Power-Down Mode with Clock
Power-Down Mode No Clock
Power Supply Rejection Ratio
OPERATING RANGE
AD9114
AD9115
AD9116
AD9117
Min Typ
Max Min Typ
Max Min Typ Max Min Typ
Max Unit
10 10 10 10 Bits
125 125 125 125 µA
VSS
VSS +
0.25
1
10
VDD
0.25
VDD
VSS
VSS +
0.25
1
10
VDD
0.25
VDD
VSS
VSS +
0.25
1
10
VDD
0.25
VDD
VSS
VSS +
0.25
1
10
VDD
0.25
VDD
V
V
Bits
0.98 1.025
10
1.08 0.98 1.025
10
1.08 0.98 1.025 1.08 0.98 1.025
10 10
1.08 V
0.1
0.1
1
1.25 0.1
1.0 0.1
1
1.25 0.1
1.0 0.1
1
1.25 0.1
1.0 0.1
1
1.25 V
1.0 V
−1 +1 −1 +1 −1 +1 −1 +1 % of FSR
1.7
3.5 1.7
3.5 1.7
3.5 1.7
3.5 V
1.7
3.5 1.7
3.5 1.7
3.5 1.7
3.5 V
1.7
1.9 1.7
1.9 1.7
1.9 1.7
1.9 V
1.7
3.5 1.7
3.5 1.7
3.5 1.7
3.5 V
220
55
10
3
8.5
3
−0.009
220
55
10
3
8.5
3
−0.009
220
55
10
3
8.5
3
−0.009
220
55
10
3
8.5
3
−0.009
mW
mA
mA
mA
mW
mW
% FSR/V
58
24
8
2
12
850
−0.007
−40 +25
+85
58
24
8
2
12
850
−0.007
−40 +25
+85
58
24
8
2
12
850
−0.007
−40 +25
+85
58
24
8
2
12
850
−0.007
−40 +25
+85
mW
mA
mA
mA
mW
µW
% FSR/V
°C
1 Based on a 1.6 kΩ external resistor for 20 mA full-scale current.
Rev. C | Page 6 of 52

6 Page









AD9115 pdf, datenblatt
AD9114/AD9115/AD9116/AD9117
Data Sheet
DB7 1
DB6 2
DB5 3
DB4 4
DVDDIO 5
DVSS 6
DVDD 7
DB3 8
DB2 9
DB1 10
PIN 1
INDICATOR
AD9115
TOP VIEW
(Not to Scale)
30 RLIN
29 IOUTN
28 IOUTP
27 RLIP
26 AVDD
25 AVSS
24 RLQP
23 QOUTP
22 QOUTN
21 RLQN
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PAD IS CONNECTED TO AVSS AND
MUST BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
Figure 3. AD9115 Pin Configuration
Table 8. AD9115 Pin Function Description
Pin No. Mnemonic
Description
1 to 4 DB[7:4]
Digital Inputs.
5
DVDDIO
Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal).
6 DVSS
Digital Common.
7 DVDD
Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD
with a 1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 to 10 DB[3:1]
Digital Inputs.
11
DB0 (LSB)
Digital Input (LSB).
12 to 15 NC
No Connect. These pins are not connected to the chip.
16 DCLKIO
Data Input/Output Clock. Clock used to qualify input data.
17 CVDD
Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18 CLKIN
LVCMOS Sampling Clock Input.
19 CVSS
Sampling Clock Supply Voltage Common.
20 CMLQ
Q DAC Output Common-Mode Level. When the internal on-chip (QRCML) is enabled, this pin is connected to
the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QRCML) is
disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor, see
the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω.
21 RLQN
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
22 QOUTN
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23 QOUTP
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
24 RLQP
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
25 AVSS
Analog Common.
26 AVDD
Analog Supply Voltage Input (1.8 V to 3.3 V).
27 RLIP
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
28 IOUTP
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29 IOUTN
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
30 RLIN
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
Rev. C | Page 12 of 52

12 Page





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