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EDD5116AGTA Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EDD5116AGTA
Beschreibung 512M bits DDR SDRAM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 30 Seiten
EDD5116AGTA Datasheet, Funktion
DATA SHEET
512M bits DDR SDRAM
EDD5108AGTA (64M words × 8 bits)
EDD5116AGTA (32M words × 16 bits)
Specifications
Density: 512M bits
Organization
16M words × 8 bits × 4 banks (EDD5108AGTA)
8M words × 16 bits × 4 banks (EDD5116AGTA)
Package: 66-pin plastic TSOP (II)
Lead-free (RoHS compliant)
Power supply: VDD, VDDQ = 2.5V ± 0.2V
Data rate: 400Mbps/333Mbps/266Mbps (max.)
Four internal banks for concurrent operation
Interface: SSTL_2
Burst lengths (BL): 2, 4, 8
Burst type (BT):
Sequential (2, 4, 8)
Interleave (2, 4, 8)
/CAS Latency (CL): 2, 2.5, 3
Precharge: auto precharge option for each burst
access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period: 7.8μs
Operating ambient temperature range
TA = 0°C to +70°C
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
Data inputs, outputs, and DM are synchronized with
DQS
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
www.DataSheet4U.com
Document No. E1191E20 (Ver. 2.0)
Date Published February 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2007-2008






EDD5116AGTA Datasheet, Funktion
EDD5108AGTA, EDD5116AGTA
DC Characteristics 1 (TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR400]
max.
Parameter
Operating current
(ACT-PRE)
Symbol
IDD0
Operating current
(ACT-READ-PRE)
IDD1
Idle power down standby
current
IDD2P
Floating idle standby current IDD2F
Quiet idle standby current IDD2Q
Active power down standby
current
IDD3P
Active standby current
IDD3N
Operating current
(Burst read operation)
Operating current
(Burst write operation)
IDD4R
IDD4W
Auto-refresh current
IDD5
Self-refresh current
Operating current
(4 banks interleaving)
IDD6
IDD7A
Grade
×8
100
120
5
20
20
30
60
150
150
175
5
300
× 16
Unit Test condition
Notes
100
mA
CKE VIH,
tRC = tRC (min.)
1, 2, 9
CKE VIH, BL = 4,
120 mA CL = 3,
1, 2, 5
tRC = tRC (min.)
5 mA CKE VIL 4
20
mA
CKE VIH, /CS VIH
DQ, DQS, DM = VREF
4, 5
20
mA
CKE VIH, /CS VIH
DQ, DQS, DM = VREF
4, 10
30 mA CKE VIL
3
60
mA
CKE VIH, /CS VIH
tRAS = tRAS (max.)
3, 5, 6
150
mA
CKE VIH, BL = 2,
CL = 3
1, 2, 5, 6
150
mA
CKE VIH, BL = 2,
CL = 3
1, 2, 5, 6
175
mA
tRFC = tRFC (min.),
Input VIL or VIH
5
mA
Input VDD – 0.2 V
Input 0.2 V
300 mA BL = 4
1, 5, 6, 7
DC Characteristics 1 (TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333, 266]
max.
Parameter
Symbol
Grade
×8
× 16 Unit Test condition
Notes
Operating current
(ACT-PRE)
IDD0
-6B 90
-7A, -7B 80
90
80
mA
CKE VIH,
tRC = tRC (min.)
1, 2, 9
Operating current
(ACT-READ-PRE)
IDD1
-6B 115
-7A, -7B 110
115
110
CKE VIH, BL = 4,
mA CL = 2.5,
1, 2, 5
tRC = tRC (min.)
www.DataSIdhleeept4oUw.ecrodmown standby
current
IDD2P
5 5 mA CKE VIL
4
Floating idle standby current IDD2F
20
20
mA
CKE VIH, /CS VIH,
DQ, DQS, DM = VREF
4, 5
Quiet idle standby current IDD2Q
20
20
mA
CKE VIH, /CS VIH,
DQ, DQS, DM = VREF
4, 10
Active power down standby
current
IDD3P
30 30 mA CKE VIL
3
Active standby current
IDD3N
55
55
mA
CKE VIH, /CS VIH
tRAS = tRAS (max.)
3, 5, 6
Operating current
(Burst read operation)
IDD4R
-6B 135
-7A, -7B 120
135
120
mA
CKE VIH, BL = 2,
CL = 2.5
1, 2, 5, 6
Operating current
(Burst write operation)
IDD4W
-6B 135
-7A, -7B 120
135
120
mA
CKE VIH, BL = 2,
CL = 2.5
1, 2, 5, 6
Auto-refresh current
IDD5
-6B 170
-7A, -7B 165
170
165
mA
tRFC = tRFC (min.),
Input VIL or VIH
Self-refresh current
IDD6
5
5
mA
Input VDD – 0.2 V
Input 0.2 V
Operating current
(4 banks interleaving)
IDD7A
300 300 mA BL = 4
1, 5, 6, 7
Data Sheet E1191E20 (Ver. 2.0)
6

6 Page









EDD5116AGTA pdf, datenblatt
EDD5108AGTA, EDD5116AGTA
Timing Parameter Measured in Clock Cycle
tCK
Parameter
Symbol
Write to pre-charge command delay
(same bank)
Read to pre-charge command delay
(same bank)
Write to read command delay
(to input all data)
Burst stop command to write
command delay
(CL = 2)
tWPD
tRPD
tWRD
tBSTW
(CL = 2.5)
tBSTW
(CL = 3)
tBSTW
Burst stop command to DQ High-Z
(CL = 2)
tBSTZ
(CL = 2.5)
tBSTZ
(CL = 3)
tBSTZ
Read command to write command
delay (to output all data)
(CL = 2)
tRWD
(CL = 2.5)
tRWD
(CL = 3)
Pre-charge command to High-Z
(CL = 2)
(CL = 2.5)
(CL = 3)
tRWD
tHZP
tHZP
tHZP
Write command to data in latency tWCD
Write recovery
tWR
DM to data in latency
tDMD
Self-refresh exit to non-read
command
tSNR
Self-refresh exit to read command tSRD
Power down entry
tPDEN
www.DataSPhoeweet4rUd.ocwomn exit to command input tPDEX
Active to Precharge command period tRAS
Active to Active/Auto-refresh
command period
Auto-refresh to Active/Auto-refresh
command period
tRC
tRFC
Active to Read/Write delay
tRCD
Precharge to active command period tRP
Number of clock cycle
5ns 6ns
min.
1 + BL/2
+ tWR
max.
min.
1 + BL/2
+ tWR
BL/2
BL/2
1 + BL/2
+ tWTR
1 + BL/2
+ tWTR
———
——3
3 —3
———
— — 2.5
333
———
——
3 + BL/2 —
——
——
33
11
3—
00
15 —
200
1
1
8
11 (-5B)
12 (-5C)
1
14
3 (-5B)
4 (-5C)
3 (-5B)
4 (-5C)
3 + BL/2
3 + BL/2
2.5
3
1
3
0
12
200
1
1
7
10
12
3
3
max.
2.5
3
2.5
3
1
0
1
7.5ns
min.
1 + BL/2
+ tWR
max.
BL/2
1 + BL/2
+ tWTR
2—
3—
3—
22
2.5 2.5
33
2 + BL/2 —
3 + BL/2 —
3 + BL/2 —
22
2.5 2.5
33
11
2—
00
10 —
200 —
11
1—
6
9
10
3
3
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Data Sheet E1191E20 (Ver. 2.0)
12

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