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WV3HG264M64EEU-D4 Schematic ( PDF Datasheet ) - White Electronic Designs

Teilenummer WV3HG264M64EEU-D4
Beschreibung 1GB - 2x64Mx64 DDR2 SDRAM UNBUFFERED
Hersteller White Electronic Designs
Logo White Electronic Designs Logo 




Gesamt 11 Seiten
WV3HG264M64EEU-D4 Datasheet, Funktion
White Electronic Designs WV3HG264M64EEU-D4
ADVANCED*
1GB – 2x64Mx64 DDR2 SDRAM UNBUFFERED
FEATURES
200-pin, dual in-line memory module (SO-DIMM)
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
Utilizes 800*, 667*, 533 and 400 Mb/s DDR2
SDRAM components
VCC = 1.8V ±0.1V
VCCSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5 and 6
Adjustable data-output drive strength
On-die termination (ODT)
Posted CAS# latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
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Dual Rank
RoHS compliant
JEDEC Package option
• 200 Pin (SO-DIMM)
• PCB – 30.00mm (1.181") TYP.
DESCRIPTION
The WV3HG264M64EEU is a 2x64Mx64 Double Data
Rate DDR2 SDRAM high density SO-DIMM. This memory
module consists of sixteen 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
200-pin SO-DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
PC2-3200
200MHz
3-3-3
OPERATING FREQUENCIES
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
February 2006
Rev. 2
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






WV3HG264M64EEU-D4 Datasheet, Funktion
White Electronic Designs WV3HG264M64EEU-D4
ADVANCED
ICC SPECIFICATION
Symbol Proposed Conditions
806 665 534 403 Units
ICC0* Operating one bank active-precharge;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD 744 704 704 mA
ICC1* Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS min(ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
TBD
864
824
824
mA
same as ICC4W
ICC2P**
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
TBD 128 128 128 mA
ICC2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
TBD 560 480 480 mA
ICC2N**
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are SWITCHING
TBD 640 560 560 mA
ICC3P**
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
TBD 480 480 480 mA
TBD 192 192 192 mA
ICC3N** Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
TBD
880
800
800
mA
SWITCHING
ICC4W*
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
TBD 1184 1024 944
wwICCw4R.D* ataOSphereaetint4gUb.ucrsotmread current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
= tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
TBD
1224 1064
944
inputs are SWITCHING; Data pattern is same as ICC4W
mA
mA
ICC5** Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
TBD 2400 2240 2240 mA
Self refresh current;
ICC6** CK and CK# at 0V; CKE 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING
Normal
TBD 128 128 128 mA
ICC7* Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK =
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid
TBD 1824 1824 1824 mA
commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
ICC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Note:
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
February 2006
Rev. 2
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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