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WV3HG128M72AER-D6 Schematic ( PDF Datasheet ) - White Electronic Designs

Teilenummer WV3HG128M72AER-D6
Beschreibung 1GB - 128Mx72 DDR2 SDRAM REGISTERED
Hersteller White Electronic Designs
Logo White Electronic Designs Logo 




Gesamt 10 Seiten
WV3HG128M72AER-D6 Datasheet, Funktion
White Electronic Designs WV3HG128M72AER-D6
ADVANCED*
1GB – 128Mx72 DDR2 SDRAM REGISTERED, w/PLL
FEATURES
240-pin, dual in-line memory module
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4300 and PC2-3200
Utilizes 800, 667, 533 and 400 MT/s DDR2 SDRAM
components
VCC = VCCQ = 1.8V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5 and 6
Adjustable data-output drive strength
On-die termination (ODT)
Posted CAS# latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
wwwP.DraotdauSchteiest4leUa.cdo-mfree
RoHS compliant
Package option
• 240 Pin DIMM
• PCB – 29.97mm (1.18") Max
DESCRIPTION
The WV3HG128M72AER is a 128Mx72 Double Data Rate
DDR2 SDRAM high density module. This memory module
consists of eighteen 128Mx4 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
PC2-3200
200MHz
3-3-3
OPERATING FREQUENCIES
PC2-4300
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
March 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






WV3HG128M72AER-D6 Datasheet, Funktion
White Electronic Designs WV3HG128M72AER-D6
ADVANCED
AC TIMING PARAMETERS
0°C ≤ TA ≤ +70°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
534
PARAMETER
Clock cycle time
CL = 4
CL = 3
CK high-level width
CK low-level width
Half clock period
DQ output access time from CK/CK#
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
A DQ and DM input pulse width (for each input)
Data hold skew factor
DQ…DQS hold, DQS to first DQ to go nonvalid, per access
DQS input high pulse width
DQS input low pulse width
DQS output access time from CK/CK#
DQS falling edge to CK rising … setup time
DQS falling edge from CK rising … hold time
DQS…DQ skew, DQS to last DQ valid, per group,
per access
DQS read preamble
DQS read postamble
DQS write preamble
DQS write postamble
www.DWaritteaScohmemeat4nUd t.ocofirmst DQS latching transition
SYMBOL
tCK (4)
tCK (3)
tCH
tCL
tHP
tAC
tHZ
tLZ
tDS
tDH
tDIPW
tQHS
tQH
tDQSH
tDQSL
tDQSCK
tDSS
tDSH
tDQSQ
tRPRE
tRPST
tWPRE
tWPST
tDQSS
MIN
3,750
5,000
0.45
0.45
MIN (tCH, tCL)
-500
tAC MIN
100
225
0.35
tHP - tQHS
0.35
0.35
-450
0.2
0.2
0.9
0.4
0.35
0.4
WL - 0.25
MAX
8,000
8,000
0.55
0.55
+500
tAC MAX
tAC MAX
400
+450
300
1.1
0.6
0.6
WL + 0.25
403
MIN MAX
5,000
5,000
8,000
8,000
0.45 0.55
0.45
MIN (tCH, tCL)
-600
tAC MIN
150
275
0.35
tHP - tQHS
0.35
0.35
-500
0.55
+600
tAC MAX
tAC MAX
450
+500
0.2
0.2
UNIT
ps
ps
tCK
tCK
ps
ps
ps
ps
ps
ps
tCK
ps
ps
tCK
tCK
ps
tCK
tCK
350 ps
0.9
0.4
0.35
0.4
WL - 0.25
1.1 tCK
0.6 tCK
tCK
0.6 tCK
WL + 0.25
tCK
Continued on next page
March 2005
Rev. 0
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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