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Teilenummer | WV3EG232M64EFSU-D4 |
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Beschreibung | 512MB - 2x32Mx64 DDR SDRAM | |
Hersteller | White Electronic Designs | |
Logo | ||
Gesamt 11 Seiten White Electronic Designs WV3EG232M64EFSU-D4
ADVANCED*
512MB – 2x32Mx64 DDR SDRAM, UNBUFFERED, w/PLL, FBGA
FEATURES
Fast data transfer rate: PC-2100 and PC-2700
Clock speeds of 133 MHz and 166 MHz
Two data transfers per clock cycle
Supports ECC error detection and correction
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2 and 2.5 (clock)
Programmable Burst Length (2, 4 or 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect (SPD) with EEPROM
Dual Rank
Power supply: VCC = VCCQ = +2.5V ±0.2V (133 and
166MHz)
Gold edge contacts
200 pin, small-outline, SO-DIMM package
• PCB height option:
31.75 mm (1.25”)
NwOwTEw: .CDoanstaulSt fahcetoeryt4foUr a.cvaoilmability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
DESCRIPTION
The WV3EG232M64EFSU is a 2x32Mx64 Double Data
Rate SDRAM memory module based on 256Mb DDR
SDRAM components. The module consists of sixteen
32Mx8 4 banks DDR SDRAMs in FBGA packages
mounted on a 200 pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR333@CL=2.5
166MHz
2.5-3-3
DDR266@CL=2
133MHz
2-2-2
DDR266@CL=2.5
133MHz
2.5-3-3
April 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs WV3EG232M64EFSU-D4
ADVANCED
AC OPERATIONG TEST CONDITIONS
VCC = 2.5V, VCCQ = 2.5V, 0°c ≤ TA ≤ +70°C
Parameter
Value
Input reference voltage for Clock
Input signal maximum peak swing
0.5 * VCCQ
1.5
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
VREF +0.31/VREF -0.31
VREF
VTT
See Load Circuit
OUTPUT LOAD CIRCUIT)
Unit
V
V
V
V
V
www.DataSheet4U.com
Output
VTT =0.5*VCCQ
RT=50Ω
Z0=50Ω
CLOAD=30pF
VREF
=0.5*VCCQ
April 2005
Rev. 0
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
6 Page | ||
Seiten | Gesamt 11 Seiten | |
PDF Download | [ WV3EG232M64EFSU-D4 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
WV3EG232M64EFSU-D4 | 512MB - 2x32Mx64 DDR SDRAM | White Electronic Designs |
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