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WV3EG216M64STSU-D4 Schematic ( PDF Datasheet ) - White Electronic Designs

Teilenummer WV3EG216M64STSU-D4
Beschreibung 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED
Hersteller White Electronic Designs
Logo White Electronic Designs Logo 




Gesamt 11 Seiten
WV3EG216M64STSU-D4 Datasheet, Funktion
White Electronic Designs WV3EG216M64STSU-D4
PRELIMINARY*
256MB – 2x16Mx64 DDR SDRAM UNBUFFERED
FEATURES
DESCRIPTION
Double-data-rate architecture
PC2700@CL=2.5
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh, (8K/64ms refresh)
Serial presence detect with EEPROM
Power Supply: VCC/VCCQ: 2.5V ± 0.20V
Dual Rank
Standard 200 pin SO-DIMM package
• Package height options:
D4: 31.75mm (1.25")
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
www.DataSheet4U.com
The WV3EG216M64STSU is a 2x16Mx64 Double
Data Rate SDRAM memory module based on 256Mb
DDR SDRAM components. The module consists of
eight 16Mx16 DDR SDRAMs in 66 pin TSOP package
mounted on a 200 Pin FR4 substrate.
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lenths allow the
same device to be useful for a variety of high bandwidth,
high performance memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
OPERATING FREQUENCIES
Clock Speed
CL-tRCD-tRP
DDR333@CL=2.5
166MHz
2.5-3-3
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






WV3EG216M64STSU-D4 Datasheet, Funktion
White Electronic Designs WV3EG216M64STSU-D4
PRELIMINARY*
Parameter
Symbol
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V
Conditions
Operating current
- One bank Active-
Precharge
IDD0* tRC = tRC(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ,DM and DQS inputs changing twice per clock cycle; address and control
inputs changing once per clock cycle
Operating current
- One bank operation
IDD1* One bank open, BL=4, Reads - Refer to the following page for detailed test
condition
Percharge power-
down standby current
IDD2P**
All banks idle; power - down mode; CKE = <VIL(max); tCK = 100Mhz for
DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM
Precharge Floating
standby current
IDD2F**
CS# > = VIH(min);All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B; Address and other control inputs
changing once per clock cycle; VIN = VREF for DQ,DQS and DM
Active power - down
standby current
IDD3P**
one bank active; power-down mode; CKE=< VIL (max); tCK = 100Mhz for
DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and
DM
Active standby
current
IDD3N**
CS# > = VIH(min); CKE> = VIH(min); one bank active; active - precharge; tRC
= tRASmax; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ, DQS and DM inputs changing twice per clock cycle; address and other
control inputs changing once per clock cycle
Operating current
- burst read
IDD4R*
Burst length = 2; reads; continguous burst; One bank active; address and
control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for
DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for
DDR266B ; 50% of data changing at every burst; lout = 0mA
Operating current
- burst write
IDD4W*
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Auto refresh current
IDD5**
Burst length = 2; writes; continuous burst; One bank active address and
control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for
DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for
DDR266B ; DQ, DM and DQS inputs changing twice per clock cycle, 50% of
input data changing at every burst
tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A &
DDR266B at 133Mhz; distributed refresh
Self refresh current;
CKE =< 0.2V
IDD6** External clock should be on; tCK = 100Mhz for DDR200, 133Mhz for
DDR266A & DDR266B
Orerating current
- Four bank operation
IDD7A*
Four bank interleaving with BL=4 -Refer to the following page for detailed test
condition
NOTE:
IDD specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different.
* Value calculated as one module rank in this operation condition and other module rank in IDD2P (CKE low) mode.
** Value calculated as all module ranks in this operation condition.
DDR333 @
CL = 2.5 Max
372
512
24
240
280
440
812
772
1440
24
1412
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2005
Rev. 0
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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