PDF WV3DG7266V-D1 Data sheet ( Hoja de datos )

Número de pieza	WV3DG7266V-D1
Descripción	512MB -2x32Mx72 SDRAM
Fabricantes	White Electronic Designs
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No Preview Available ! White Electronic Designs WV3DG7266V-D1 PRELIMINARY* 512MB – 2x32Mx72 SDRAM, UNBUFFERED, w/PLL FEATURES DESCRIPTION PC100 and PC133 Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs The WV3DG7266V is a 2x32Mx72 synchronous DRAM module which consists of nine stacked 64Mx8 with 4 banks SDRAM components in TSOP II package, and one 2Kb EEPROM for Serial Presence Detect which are mounted on a 144 pin SO-DIMM multilayer FR4 Substrate. Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 or Full Page 3.3V ± 0.3V Power Supply * This product is under development, is not qualiﬁed or characterized and is subject to change without notice. NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option Dual Rank 144 Pin SO-DIMM JEDEC • PCB: 31.75mm (1.25”) PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE) PINOUT PIN FRONT PIN BACK 1 VSS 2 VSS 3 DQ0 4 DQ32 5 DQ1 6 DQ33 7 DQ2 8 DQ34 9 DQ3 10 DQ35 w1w1 w.DaVtCaCShee12t4U.cVoCmC 13 DQ4 14 DQ36 15 DQ5 16 DQ37 17 DQ6 18 DQ38 19 DQ7 20 DQ39 21 VSS 22 VSS 23 DQM0 24 DQM4 25 DQM1 26 DQM5 27 VCC 28 VCC 29 A0 30 A3 31 A1 32 A4 33 A2 34 A5 35 VSS 36 VSS 37 DQ8 38 DQ40 39 DQ9 40 DQ41 41 DQ10 42 DQ42 43 DQ11 44 DQ43 45 VCC 46 VCC 47 DQ12 48 DQ44 PIN FRONT PIN 49 DQ13 50 51 DQ14 52 53 DQ15 54 55 VSS 56 57 CB0 58 59 CB1 60 61 CLK0 62 63 VCC 64 65 RAS# 66 67 WE# 68 69 CS0# 70 71 CS1#* 72 73 NC 74 75 VSS 76 77 CB2 78 79 CB3 80 81 VCC 82 83 DQ16 84 85 DQ17 86 87 DQ18 88 89 DQ19 90 91 VSS 92 93 DQ20 94 95 DQ21 96 BACK DQ45 DQ46 DQ47 VSS CB4 CB5 CKE0 VCC CAS# CKE1 A12 NC CLK1 VSS CB6 CB7 VCC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 PIN FRONT PIN 97 DQ22 98 99 DQ23 100 101 VCC 102 103 A6 104 105 A8 106 107 VSS 108 109 A9 110 111 A10 112 113 VCC 114 115 DQM2 116 117 DQM3 118 119 VSS 120 121 DQ24 122 123 DQ25 124 125 DQ26 126 127 DQ27 128 129 VCC 130 131 DQ28 132 133 DQ29 134 135 DQ30 136 137 DQ31 138 139 VSS 140 141 SDA 142 143 VCC 144 BACK DQ54 DQ55 VCC A7 BA0 VSS BA1 A11 VCC DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS SCL VCC PIN NAMES A0 – A12 BA0-1 DQ0-63 CLK0, CLK1 CB0-7 CKE0 CS0#, CS1# RAS# CAS# WE# DQM0-7 VCC VSS SDA SCL DNU NC Address Input (Multiplexed) Select Bank Data Input/Output Clock Input Check Bit (Data-In/Data-Out) Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe #Write Enable DQM Power Supply (3.3V) Ground Serial Data I/O Serial Clock Do Not Use No Connect * These pins are not used in this module ** These pins should be NC in the system which does not support SPD. August 2005 Rev. 1 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs WV3DG7266V-D1 PRELIMINARY Parameter AC input levels (VIH/VIL) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition AC OPERATING TEST CONDITIONS VCC = 3.3v, 0°C - 70°C Value 2.4/0.4 1.4 tR/tF = 1/1 1.4 See Fig. 2 Unit V V ns V DC OUTPUT LOAD CIRCUIT AC OUTPUT LOAD CIRCUIT Output 870Ω 3.3V 1200Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA 50pF Output Z0 = 50Ω Vtt = 1.4V 50Ω 50pF OPERATING AC PARAMETER Parameter www.DataSheet4U.com Row active to row active delay RAS# to CAS# delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 Version 7 75 10 15 15 20 15 20 20 15 20 20 45 45 50 100 60 65 70 2 2 CLK + tRP 1 1 1 2 1 Unit ns ns ns ns us ns CLK — CLK CLK CLK ea Notes: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. Note 1 1 1 1 1 2 2 2 3 4 August 2005 Rev. 1 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page

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