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P89LPC916 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P89LPC916
Beschreibung (P89LPC915 - P89LPC917) 8-bit microcontrollers
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
P89LPC916 Datasheet, Funktion
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
2 kB 3 V Flash with 8-bit A/D converter
Rev. 04 — 17 December 2004
Product data
1. General description
The P89LPC915/916/917 are single-chip microcontrollers in low-cost 14-pin and
16-pin packages, based on a high performance processor architecture that executes
instructions in two to four clocks, six times the rate of standard 80C51 devices. Many
system level functions have been incorporated into the P89LPC915/916/917 in order
to reduce component count, board space, and system cost.
2. Features
www.DataSheet4U.com
s 2 kB byte-erasable Flash code memory organized into 256-byte sectors and
16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile
data storage.
s 256-byte RAM data memory.
s Two 16-bit counter/timers. Timer 0 (and Timer 1 - P89LPC917) may be configured
to toggle a port output upon timer overflow or to become a PWM output.
s 23-bit system timer that can also be used as a Real-Time clock.
s 4-input multiplexed 8-bit A/D converter/single DAC output. Two analog
comparators with selectable reference.
s Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities.
s SPI communication port (P89LPC916).
s Internal RC oscillator option allows operation without external oscillator
components. The RC oscillator (factory calibrated to ±1 %) option is selectable
and fine tunable.
s 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
s Up to 14 I/O pins when using internal oscillator and reset options (P89LPC916,
P89LPC917).
3. Additional features
14-pin (P89LPC915) and 16-pin (P89LPC916, P89LPC917) TSSOP packages.
A high performance 80C51 CPU provides instruction cycle times of 111 ns to
222 ns for all instructions except multiply and divide when executing at 18 MHz.
This is six times the performance of the standard 80C51 running at the same clock
frequency. A lower clock frequency for the same performance results in power
savings and reduced EMI.






P89LPC916 Datasheet, Funktion
Philips Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
www.DataSheet4U.com
P89LPC917
HIGH PERFORMANCE
ACCELERATED 2-CLOCK 80C51 CPU
2 kB
CODE FLASH
256-BYTE
DATA RAM
INTERNAL
BUS
PORT 2
CONFIGURABLE I/Os
PORT 1
CONFIGURABLE I/Os
PORT 0
CONFIGURABLE I/Os
KEYPAD
INTERRUPT
WATCHDOG TIMER
AND OSCILLATOR
UART
I2C
ADC1/DAC1
REAL-TIME CLOCK/
SYSTEM TIMER
TIMER 0
TIMER 1
ANALOG
COMPARATORS
external
clock
input
CLKOUT
PROGRAMMABLE
OSCILLATOR DIVIDER
CPU
CLOCK
ON-CHIP RC
OSCILLATOR
Fig 3. P89LPC917 block diagram.
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
002aaa824
9397 750 14397
Product data
Rev. 04 — 17 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6 of 72

6 Page









P89LPC916 pdf, datenblatt
Philips Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 4: P89LPC916 pin description…continued
Symbol
Pin
Type Description
P2.2 to P2.5
I/O Port 2: Port 2 is a 4-bit I/O port having user-configurable output types. During reset
Port 1 latches are configured in the input only mode with the internal pull-up disabled.
The operation of the P2 input and outputs depends upon the port configuration
selected. Refer to Section 9.12.1 “Port configurations” and Table 13 “DC electrical
characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described below:
6 I/O P2.2 — Port 2 bit 2.
O MOSI — SPI master out slave in. When configured as a master this pin is an output.
When configured as a slave, this pin is an input.
5 I/O P2.3 — Port 2 bit 3.
I MISO — SPI master in slave out. When configured as a master this pin is an input.
When configured as a slave, this pin is an output.
2 I/O P2.4 — Port 2 bit 4.
I/O SS — SPI Slave select.
11 I/O P2.5 — Port 2 bit 5.
I/O SPICLK — When configured as a master this pin is an output. When configured as a
slave, this pin is an input.
VSS 4 I Ground: 0 V reference.
VDD 12 I Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.
www.DataSheet4U.com
9397 750 14397
Product data
Rev. 04 — 17 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12 of 72

12 Page





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