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P89LPC914 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P89LPC914
Beschreibung (P89LPC912 - P89LPC914) 8-bit microcontrollers
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 63 Seiten
P89LPC914 Datasheet, Funktion
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
1 kB 3 V Flash with 128-byte RAM
Rev. 03 — 17 December 2004
Product data
1. General description
The P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin
packages, based on a high performance processor architecture that executes
instructions in two to four clocks, six times the rate of standard 80C51 devices. Many
system level functions have been incorporated into the P89LPC912/913/914 in order
to reduce component count, board space, and system cost.
2. Features
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s 1 kB byte-erasable Flash code memory organized into 256-byte sectors and
16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile
data storage.
s 128-byte RAM data memory.
s Two 16-bit counter/timers. Each timer may be configured to toggle a port output
upon timer overflow or to become a PWM output.
s 23-bit system timer that can also be used as a Real-Time clock.
s Two analog comparators with selectable inputs and reference source.
s Enhanced UART with fractional baudrate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities
(P89LPC913, P89LPC914).
s SPI communication port.
s Internal RC oscillator (factory calibrated to ±1 %) option allows operation without
external oscillator components. The RC oscillator option is selectable and fine
tunable.
s 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
s Up to 12 I/O pins when using internal oscillator and reset options.
3. Additional features
14-pin TSSOP packages.
A high performance 80C51 CPU provides instruction cycle times of 111 ns to
222 ns for all instructions except multiply and divide when executing at 18 MHz
(167 ns to 333 ns at 12 MHz). This is six times the performance of the standard
80C51 running at the same clock frequency. A lower clock frequency for the same
performance results in power savings and reduced EMI.
In-Application Programming (IAP-Lite) and byte erase allows code memory to be
used for non-volatile data storage.






P89LPC914 Datasheet, Funktion
Philips Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
www.DataSheet4U.com
P89LPC914
HIGH PERFORMANCE
ACCELERATED 2-CLOCK 80C51 CPU
1 kB
CODE FLASH
128-BYTE
DATA RAM
INTERNAL BUS
PORT 2
CONFIGURABLE I/Os
PORT 1
CONFIGURABLE I/Os
PORT 0
CONFIGURABLE I/Os
KEYPAD
INTERRUPT
PROGRAMMABLE
OSCILLATOR DIVIDER
CPU
CLOCK
ON-CHIP
RC
OSCILLATOR
Fig 3. P89LPC914 block diagram.
UART
SPI
REAL-TIME CLOCK/
SYSTEM TIMER
TIMER 0
TIMER 1
WATCHDOG TIMER
AND OSCILLATOR
ANALOG
COMPARATORS
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
002aaa474
9397 750 14468
Product data
Rev. 03 — 17 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6 of 63

6 Page









P89LPC914 pdf, datenblatt
Philips Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
Table 5: P89LPC914 pin description
Symbol
Pin
Type Description
P0.2,
P0.4 to P0.6
I/O Port 0: Port 0 is a 4-bit I/O port with a user-configurable output type. During reset
Port 0 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 0 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to Section
9.11.1 “Port configurations” and Table 13 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
13 I/O P0.2 — Port 0 bit 2.
I CIN2A — Comparator 2 positive input A.
I KBI2 — Keyboard input 2.
12 I/O P0.4 — Port 0 bit 4.
I CIN1A — Comparator 1 positive input A.
I KBI4 — Keyboard input 4.
11 I/O P0.5 — Port 0 bit 5.
I CMPREF — Comparator reference (negative) input.
I KBI5 — Keyboard input 5.
5 I/O P0.6 — Port 0 bit 6.
O CMP1 — Comparator 1 output.
I KBI6 — Keyboard input 6.
P1.0 to P1.2,
P1.5
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I/O
(P1.0 to
P1.2);
I (P1.5)
Port 1: Port 1 is a 4-bit I/O port with a user-configurable output type, except for
three pins noted below. During reset Port 1 latches are configured in the input only
mode with the internal pull-up disabled. The operation of the configurable Port 1
pins as inputs and outputs depends upon the port configuration selected. Each of
the configurable port pins are programmed independently. Refer to Section 9.11.1
“Port configurations” and Table 13 “DC electrical characteristics” for details. P1.2 is
an open drain when used as an output. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
9 I/O P1.0 — Port 1 bit 0.
O TxD — Transmitter output for the serial port.
6 I/O P1.1 — Port 1 bit 1.
I RxD — Receiver input for the serial port.
7 I/O P1.2 — Port 1 bit 2. (Open drain when used as an output.)
I/O T0 — Timer/counter 0 external count input or overflow output. (Open drain when
used as outputs.)
3 I P1.5 — Port 1 bit 5 (input only).
I RST — External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input, a LOW on this pin resets the microcontroller, causing
I/O ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force In-System
Programming mode.
9397 750 14468
Product data
Rev. 03 — 17 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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