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ADF4350 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF4350
Beschreibung Wideband Synthesizer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADF4350 Datasheet, Funktion
Data Sheet
Wideband Synthesizer with Integrated VCO
ADF4350
FEATURES
GENERAL DESCRIPTION
Output frequency range: 137.5 MHz to 4400 MHz
The ADF4350 allows implementation of fractional-N or
Fractional-N synthesizer and integer-N synthesizer
integer-N phase-locked loop (PLL) frequency synthesizers
Low phase noise VCO
if used with an external loop filter and external reference
Programmable divide-by-1/-2/-4/-8/-16 output
frequency.
Typical rms jitter: <0.4 ps rms
Power supply: 3.0 V to 3.6 V
Logic compatibility: 1.8 V
Programmable dual-modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
Switched bandwidth fast-lock mode
Cycle slip reduction
APPLICATIONS
The ADF4350 has an integrated voltage controlled oscillator
(VCO) with a fundamental output frequency ranging from
2200 MHz to 4400 MHz. In addition, divide-by-1/2/4/8 or 16
circuits allow the user to generate RF output frequencies as low
as 137.5 MHz. For applications that require isolation, the RF
output stage can be muted. The mute function is both pin- and
software-controllable. An auxiliary RF output is also available,
which can be powered down if not in use.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX,
GSM, PCS, DCS, DECT)
Test equipment
Wireless LANs, CATV equipment
Clock generation
FUNCTIONAL BLOCK DIAGRAM
SDVDD
AVDD
DVDD
VP RSET VVCO
REFIN
CLK
DATA
LE
×2
DOUBLER
10-BIT R
COUNTER
÷2
DIVIDER
DATA REGISTER
FUNCTION
LATCH
INTEGER FRACTION MODULUS
REG
REG
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
LOCK
DETECT
MULTIPLEXER
CHARGE
PUMP
PHASE
COMPARATOR
VCO
CORE
FLO SWITCH
÷1/2/4/8/16
OUTPUT
STAGE
OUTPUT
STAGE
MUXOUT
SW
LD
CPOUT
VTUNE
VREF
VCOM
TEMP
RFOUTA+
RFOUTA–
PDBRF
RFOUTB+
RFOUTB–
CE AGND
DGND
CPGND
Figure 1.
MULTIPLEXER
SDGND AGNDVCO
ADF4350
Rev. B
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Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved.
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ADF4350 Datasheet, Funktion
Data Sheet
ADF4350
TIMING CHARACTERISTICS
AVDD = DVDD = VVCO = SDVDD = VP = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless
otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit (B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
CLK
t4 t5
DATA
DB31 (MSB)
t2 t3
DB30
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
LE
t1
LE
Figure 2. Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Rev. B | Page 5 of 34

6 Page









ADF4350 pdf, datenblatt
Data Sheet
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
during power-down.
POWER-DOWN
CONTROL
NC 100k
REFIN NC
SW2
SW1
SW3
NO
TO R COUNTER
BUFFER
Figure 16. Reference Input Stage
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. The division ratio is determined by INT, FRAC and MOD
values, which build up this divider.
INT, FRAC, MOD, AND R COUNTER RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies
that are spaced by fractions of the PFD frequency. See the RF
Synthesizer—A Worked Example section for more information.
The RF VCO frequency (RFOUT) equation is
RFOUT = fPFD × (INT + (FRAC/MOD))
(1)
where RFOUT is the output frequency of external voltage
controlled oscillator (VCO).
INT is the preset divide ratio of the binary 16-bit counter
(23 to 65535 for 4/5 prescaler, 75 to 65,535 for 8/9 prescaler).
MOD is the preset fractional modulus (2 to 4095).
FRAC is the numerator of the fractional division (0 to MOD − 1).
fPFD = REFIN × [(1 + D)/(R × (1 + T))]
(2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
T is the REFIN divide-by-2 bit (0 or 1).
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
ADF4350
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
RF N DIVIDER
N COUNTER
INT
REG
N = INT + FRAC/MOD
TO PFD
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
MOD
REG
FRAC
VALUE
Figure 17. RF INT Divider
INT N MODE
If the FRAC = 0 and DB8 in Register 2 (LDF) is set to 1, the
synthesizer operates in integer-N mode. The DB8 in Register 2
(LDF) must be set to 1 to get integer-N digital lock detect.
R COUNTER
The 10–bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock
to the PFD. Division ratios from 1 to 1023 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The phase frequency detector (PFD) takes inputs from the
R counter and N counter and produces an output proportional
to the phase and frequency difference between them. Figure 18
is a simplified schematic of the phase frequency detector. The
PFD includes a fixed delay element that sets the width of the
antibacklash pulse, which is typically 3 ns. This pulse ensures
there is no dead zone in the PFD transfer function, and gives a
consistent reference spur level.
HIGH
UP
D1 Q1
U1
+IN CLR1
DELAY
U3
CHARGE
PUMP
CP
HIGH
–IN
CLR2 DOWN
D2 Q2
U2
Figure 18. PFD Simplified Schematic
Rev. B | Page 11 of 34

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