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PE3341 Schematic ( PDF Datasheet ) - Peregrine Semiconductor

Teilenummer PE3341
Beschreibung Integer-N PLL
Hersteller Peregrine Semiconductor
Logo Peregrine Semiconductor Logo 




Gesamt 17 Seiten
PE3341 Datasheet, Funktion
Product Description
The PE3341 is a high performance integer-N PLL with
embedded EEPROM capable of frequency synthesis up to
2700 MHz with a speed-grade option to 3000 MHz. The
EEPROM allows designers to permanently store control bits,
allowing easy configuration of self-starting synthesizers. The
superior phase noise performance of the PE3341 is ideal for
applications such as sonet, wireless base stations, fixed
wireless, and RF instrumentation systems.
The PE3341 features a ÷10/11 dual modulus prescaler,
counters, a phase comparator, and a charge pump as shown in
Figure 1. Counter values are programmable through a three-
wire serial interface.
The PE3341 UltraCMOS™ Phase Locked-Loop is
manufactured in Peregrine’s patented Ultra Thin Silicon
(UTSi®) CMOS process, offering excellent RF performance
with the economy and integration of conventional CMOS.
Product Specification
PE3341
2700 MHz Integer-N PLL
with Field-Programmable EEPROM
Features
Field-programmable EEPROM for self-
starting applications
Standard 2700 MHz operation,
3000 MHz speed-grade option
÷10/11 dual modulus prescaler
Internal charge pump
Serial programmable
Low power — 20 mA at 3 V
Ultra-low phase noise
Available in 24-lead TSSOP or 20-lead
4x4 mm QFN package
Figure 1. Block Diagram
Fin
Fin
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E_W R
Data
Clock
Serial
Interface
Mux
EELoad
VPP
S_W R
fr
EESel
FSel
Enhancem ent
Register
(8-bit)
Primary
Register
(20-bit)
EE
Register
(20-bit)
20
Transfer
Logic
Prescaler
÷10/11
Secondary
Register
(20-bit)
20
20
EEPROM
M Counter
÷2 to ÷512
13
6
6
R Counter
÷1 to ÷64
Phase
Detector
PD_U
PD_D
Charge
Pump
2k
CP
LD
Cext
Document No. 70-0053-04 www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 17






PE3341 Datasheet, Funktion
Functional Description
The PE3341 consists of a dual modulus prescaler,
three programmable counters, a phase detector
with charge pump and control logic with EEPROM
memory (see Figure 1).
The dual modulus prescaler divides the VCO
frequency by either 10 or 11, depending on the
state of the internal modulus select logic. The R
and M counters divide the reference and prescaler
outputs by integer values stored in one of three
selectable registers. The modulus select logic
uses the 4-bit A counter.
The phase-frequency detector generates up and
down frequency control signals that direct the
charge pump operation, and are also used to
enable a lock detect circuit.
Frequency control data is loaded into the device
via the Serial Data Port, and can be placed in
three separate frequency registers. One of these
registers (EE register) is used to load from and
write to the non-volatile 20-bit EEPROM.
Various operational and test modes are available
through the enhancement register, which is only
accessible through the Serial Data Port (it cannot
be loaded from the EEPROM).
Main Counter Chain
wwTwh.DeatamSaheinet4cUo.cuonmter chain divides the RF input
frequency, Fin, by an integer derived from the
user-defined values in the M and A counters. It
operates in two modes:
High Frequency Mode
Setting PB (prescaler bypass) LOW enables the
÷10/11 prescaler, providing operation to 2.7 GHz.
In this mode, the output from the main counter
chain, fp, is related to the VCO frequency, Fin, by
the following equation:
fp = Fin / [10 x (M + 1) + A]
(1)
where 0 A 15 and A M + 1; 1 M 511
When the loop is locked, Fin is related to the
reference frequency, fr, by the following equation:
Fin = [10 x (M + 1) + A] x (fr / (R+1))
(2)
where 0 A 15 and A M + 1; 1 M 511
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 17
PE3341
Product Specification
A consequence of the upper limit on A is that Fin
must be greater than or equal to 90 x (fr / (R+1)) to
obtain contiguous channels. Programming the M
counter with the minimum value of 1 will result in a
minimum M counter divide ratio of 2.
Programming the M and A counters with their
maximum values provides a divide ratio of 5135.
Prescaler Bypass Mode
Setting the PB bit of a frequency register HIGH
allows Fin to bypass the ÷10/11 prescaler. In this
mode, the prescaler and A counter are powered
down, and the input VCO frequency is divided by
the M counter directly. The following equation
relates Fin to the reference frequency fr:
Fin = (M + 1) x (fr / (R+1))
where 1 M 511
(3)
Reference Counter
The reference counter chain divides the reference
frequency, fr, down to the phase detector
comparison frequency, fc.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the following
equation:
fc = fr / (R + 1)
where 0 R 63
(4)
Note that programming R with 0 will pass the
reference frequency, fr, directly to the phase
detector.
Phase Detector and Charge Pump
The phase detector is triggered by rising edges
from the main counter (fp) and the reference
counter (fc). It has two outputs, PD_U, and PD_D.
If the divided VCO leads the divided reference in
phase or frequency (fp leads fc), PD_D pulses
LOW. If the divided reference leads the divided
VCO in phase or frequency (fc leads fp), PD_U
pulses LOW. The width of either pulse is directly
proportional to the phase offset between the fp and
fc signals.
The signals from the phase detector are also
routed to an internal charge pump. PD_U controls
a current source at pin CP, and PD_D controls a
current sink at pin CP. When using a positive Kv
VCO, PD_U pulses (current source) will increase
the VCO frequency, and PD_D pulses (current
sink) will decrease VCO frequency.
Document No. 70-0053-04 UltraCMOS™ RFIC Solutions

6 Page









PE3341 pdf, datenblatt
PE3341
Product Specification
Figure 8. Details of EE register contents loaded from EEPROM and then shifted out Serially through
Dout pin - The procedure is performed twice.
EELoad
EESel
3V
0V
3V
0V
S_WR
0V
E_WR
Data
Clock
Dout
(example)
3V
0V
3V
0V
3V
0V
3V
0 1010011111000111001
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0V
Enhancement
Register
Programming
EE Register
load from
EEPROM
EE Register
shifted out
through Dout
Rough time scale 20 us
Note: ENH/ ( Pin 3 in TSSOP or Pin 20 in QFN) is at low (0) for this process.
In Figure 8, the first step is to program
Enhancement Register to set Bit 1 high (“1”) to
access EE Register Output Bit Function.
Subsequent action, which includes pulses, allows
the existing EE Register contents to be shifted out
the Dout pin and the EEPROM contents are
loaded to the EE Register. Since the initial data
existing in the EE Register could be anything, the
data must be flushed out before clocking the
contents of the EEPROM register out. After the
same procedures are duplicated, the Dout output
is the EEPROM content. Note that only 19 Clock
pulses are enough for the 20-bit EE Register
because the first bit data is already present at
Dout pin. Also ENH/ (Pin 3 in TSSOP or Pin 20 in
QFN) is set to low (“0”) to access the
Enhancement mode.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 12 of 17
Document No. 70-0053-04 UltraCMOS™ RFIC Solutions

12 Page





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