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PDF PE3336 Data sheet ( Hoja de datos )
| Número de pieza | PE3336 | |
| Descripción | Integer-N PLL | |
| Fabricantes | Peregrine Semiconductor | |
| Logotipo |  |
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Product Description
Peregrine’s PE3336 is a high performance integer-N PLL
capable of frequency synthesis up to 3000 MHz. The
superior phase noise performance of the PE3336 makes it
ideal for applications such as LMDS / MMDS / WLL
basestations and demanding terrestrial systems.
The PE3336 features a 10/11 dual modulus prescaler,
counters and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial or
parallel interface and can also be directly hard wired.
The PE3336 Phase Locked-Loop is optimized for terrestrial
applications. It is manufactured on Peregrine’s
UltraCMOS™ process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering
the performance of GaAs with the economy and integration
of conventional CMOS.
Product Specification
PE3336
3000 MHz UltraCMOS™ Integer-N PLL
for Low Phase Noise Applications
Features
• 3000 MHz operation
• ÷10/11 dual modulus prescaler
• Internal phase detector
• Serial, parallel or hardwired
programmable
• Pin compatible with PE3236
• Ultra-low phase noise
• Available in 44-lead PLCC and
7x7 mm 48-lead QFN package
Figure 1. Block Diagram
Fin
www.DaFtaiSn heet4U.com
Prescaler
10 / 11
D(7:0)
8
Sdata
Primary
20-bit
Latch 20
Pre_en
M(6:0)
A(3:0)
R(3:0)
fr
Secon-
dary
20-bit
Latch
20
20
20
16
Main
Counter
13
66
R Counter
fp
Phase
Detector
PD_U
PD_D
fc
Document No. 70-0033-02 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 15
1 page  
PE3336
Product Specification
Table 2. Absolute Maximum Ratings
Symbol
VDD
VI
Parameter/Conditions Min Max Units
Supply voltage
Voltage on any input
-0.3 4.0
-0.3 VDD
V
V
II DC into any input
IO DC into any output
Tstg Storage temperature
-10 +10
-10 +10
-65 150
mA
mA
°C
Table 3. Operating Ratings
Symbol
VDD
TA
Parameter/Conditions
Supply voltage
Operating ambient
Min
2.85
-40
Max
3.15
85
Units
V
°C
Table 4. ESD Ratings
Symbol
VESD
Parameter/Conditions
ESD voltage (Human Body
Level
1000
Units
V
Note 1: Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
IDD Operational supply current;
Prescaler disabled
Prescaler enabled
Digital Inputs: All except fr, R0, Fin, Fin
Conditions
VDD = 2.85 to 3.15 V
Min Typ
10
19
VIH High level input voltage
VDD = 2.85 to 3.15 V
0.7 x VDD
VIL Low level input voltage
VDD = 2.85 to 3.15 V
www.DataIISH heet4U.cHoimgh level input current
IIL Low level input current
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
-1
Reference Divider input: fr
IIHR High level input current
VIH = VDD = 3.15 V
IILR Low level input current
VIL = 0, VDD = 3.15 V
-100
R0 Input (Pull-up Resistor): R0
IIHRO High level input current
VIH = VDD = 3.15 V
IILRO Low level input current
Counter and phase detector outputs: fc, fp, PD_D, PD_U
VIL = 0, VDD = 3.15 V
-5
VOLD
Output voltage LOW
Iout = 6 mA
VOHD
Output voltage HIGH
Iout = -3 mA
VDD - 0.4
Lock detect outputs: Cext, LD
VOLC
Output voltage LOW, Cext
Iout = 100 mA
VOHC
Output voltage HIGH, Cext
Iout = -100 mA
VDD - 0.4
VOLLD
Output voltage LOW, LD
Iout = 6 mA
Max
26
Units
mA
mA
0.3 x VDD
+70
V
V
µA
µA
+100
µA
µA
+5 µA
µA
0.4 V
V
0.4 V
V
0.4 V
Document No. 70-0033-02 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 15
5 Page 
PE3336
Product Specification
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Reserved**
Reserved**
Reserved**
Power down
Counter load
Power down of all functions except programming interface.
Immediate and continuous load of counter programming as directed by the Bmode and
Bit 5
MSEL output
Bit 6
Bit 7
Prescaler output
fp, fc OE
** Program to 0
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Drives the raw internal prescaler output onto the Dout output.
fp, fc outputs disabled.
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, PD_U, and PD_D.
If the divided VCO leads the divided reference in
phase or frequency (fp leads fc), PD_D pulses
“low”. If the divided reference leads the divided
VCO in phase or frequency (fc leads fp), PD_U
pulses “low”. The width of either pulse is directly
wwpwr.DoaptaoSrhtieoent4aUl.ctoomphase offset between the two input
signals, fp and fc.
The phase detector gain is equal to 2.7 V / 2 π,
which numerically yields 0.43 V / radian.
PD_U and PD_D drive an active loop filter which
controls the VCO tune voltage. PD_U pulses
result in an increase in VCO frequency; PD_D
pulses result in a decrease in VCO frequency (for
a positive Kv VCO).
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 kohm resistor. Connecting Cext to an external
shunt capacitor provides low pass filtering of this
signal. Cext also drives the input of an internal
inverting comparator with an open drain output.
Thus LD is an “AND” function of PD_U and PD_D.
Document No. 70-0033-02 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 15
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| PDF Descargar | [ Datasheet PE3336.PDF ] | |
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