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PDF PE3335 Data sheet ( Hoja de datos )
| Número de pieza | PE3335 | |
| Descripción | Integer-N PLL | |
| Fabricantes | Peregrine Semiconductor | |
| Logotipo |  |
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Product Description
Peregrine’s PE3335 is a high performance integer-N PLL
capable of frequency synthesis up to 3000 MHz. The
superior phase noise performance of the PE3335 makes it
ideal for applications such as LMDS / MMDS / WLL
basestations and demanding terrestrial systems.
The PE3335 features a 10/11 dual modulus prescaler,
counters, phase comparator and a charge pump as shown
in Figure 1. Counter values are programmable through
either a serial or parallel interface and can also be directly
hard wired.
The PE3335 Phase Locked-Loop is optimized for terrestrial
applications. It is manufactured on Peregrine’s
UltraCMOS™ process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering
the performance of GaAs with the economy and integration
of conventional CMOS.
Figure 1. Block Diagram
Fin
www.DFatinaSheet4U.com
Prescaler
10/11
D(7:0)
8
Sdata
Primary
20-bit
Latch 20
Pre_en
M(6:0)
A(3:0)
R(3:0)
fr
Secon-
dary
20-bit
Latch
20
20
20
16
Main
Counter
13
66
R Counter
Product Specification
PE3335
3000 MHz UltraCMOS™ Integer-N PLL
for Low Phase Noise Applications
Features
• 3000 MHz operation
• ÷10/11 dual modulus prescaler
• Internal phase detector with
charge pump
• Serial, parallel or hardwired
programmable
• Ultra-low phase noise
• Available in 44-lead PLCC and
7x7 mm 48-lead QFN packages
fp
PD_U
Phase
Detector
PD_D
Charge
Pump
CP
fc
Document No. 70-0049-02 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 15
1 page  
PE3335
Product Specification
Table 2. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max
VDD Supply voltage
VI Voltage on any input
II DC into any input
-0.3 4.0
-0.3 VDD +
0.3
-10 +10
IO DC into any output
-10 +10
Tstg Storage temperature range -65 150
Units
V
V
mA
mA
°C
Table 3. Operating Ratings
Symbol Parameter/Conditions Min Max Units
VDD Supply voltage
2.85 3.15
V
TA Operating ambient
temperature range
-40 85
°C
Table 4. ESD Ratings
Symbol Parameter/Conditions
VESD
ESD voltage (Human Body
Level
1000
Units
V
Note 1: Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
IDD Operational supply current;
Prescaler disabled
Prescaler enabled
Digital Inputs: All except fr, R0, Fin, Fin
VIH High level input voltage
VIL Low level input voltage
IIH High level input current
IIL Low level input current
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IIHR High level input current
IILR Low level input current
R0 Input (Pull-up Resistor): R0
IIHRO High level input current
IILRO Low level input current
Counter output Dout
VOLD
Output voltage LOW
VOHD
Output voltage HIGH
Lock detect outputs: Cext, LD
VOLC
Output voltage LOW, Cext
VOHC
Output voltage HIGH, Cext
VOLLD
Output voltage LOW, LD
Charge Pump output: CP
ICP - Source Drive current
ICP – Sink Drive current
ICPL Leakage current
ICP – Source Sink vs. source mismatch
vs. ICP Sink
ICP vs. VCP Output current magnitude variation vs. voltage
Conditions
VDD = 2.85 to 3.15 V
VDD = 2.85 to 3.15 V
VDD = 2.85 to 3.15 V
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
Iout = 6 mA
Iout = -3 mA
Iout = 100 mA
Iout = -100 mA
Iout = 6 mA
VCP = VDD / 2
VCP = VDD / 2
1.0 V < VCP < VDD – 1.0 V
VCP = VDD / 2,
TA = 25° C
V < VCP < VDD – 1.0 V
TA = 25° C
Min
0.7 x VDD
Typ
10
24
-1
-100
-5
VDD - 0.4
VDD - 0.4
-2.6 -2
1.4 2
-1 1
Max
31
Units
mA
mA
0.3 x VDD
+70
+100
+5
0.4
0.4
0.4
-1.4
2.6
15
15
V
V
µA
µA
µA
µA
µA
µA
V
V
V
V
V
mA
mA
µA
%
%
Document No. 70-0049-02 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 15
5 Page 
PE3335
Product Specification
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Reserved**
Reserved**
Reserved**
Power down
Counter load
Power down of all functions except programming interface.
Immediate and continuous load of counter programming as directed by the Bmode and
Bit 5
Bit 6
Bit 7
MSEL output
Prescaler output
fp, fc OE
** Program to 0
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Drives the raw internal prescaler output onto the Dout output.
fp, fc outputs disabled.
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, PD_U, and PD_D.
If the divided VCO leads the divided reference in
phase or frequency (fp leads fc), PD_D pulses
“low”. If the divided reference leads the divided
VCO in phase or frequency (fc leads fp), PD_U
pulses “low”. The width of either pulse is directly
wwpwr.DoaptaoSrhtieoent4aUl.ctoomphase offset between the two input
signals, fp and fc.
The signals from the phase detector couple
directly to a charge pump. PD_U controls a
current source at pin CP with constant amplitude
and pulse duration approximately the same as
PD_U. PD_D similarly drives a current sink at pin
CP. The current pulses from pin CP are low pass
filtered externally and then connected to the VCO
tune voltage. PD_U pulses result in a current
source, which increases the VCO frequency;
PD_D pulses result in a current sink, which
decreases VCO frequency (for a positive Kv
VCO).
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 kohm resistor. Connecting Cext to an external
shunt capacitor provides low pass filtering of this
signal. Cext also drives the input of an internal
inverting comparator with an open drain output.
Thus LD is an “AND” function of PD_U and PD_D.
Document No. 70-0049-02 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet PE3335.PDF ] | |
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