Datenblatt-pdf.com


AD8120 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD8120
Beschreibung Triple Skew-Compensating Video Delay Line
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 17 Seiten
AD8120 Datasheet, Funktion
Data Sheet
Triple Skew-Compensating Video Delay
Line with Analog and Digital Control
AD8120
FEATURES
Corrects for unshielded twisted pair (UTP) cable skew
Delay of up to 50 ns per channel
High speed
200 MHz BW @ VOUT = 1.4 V p-p and 0 ns delay
150 MHz BW @ VOUT = 1.4 V p-p and 50 ns delay
Excellent channel-to-channel matching
30 mV offset matching RTI
0.8% gain matching
Low output offset
±30 mV RTI
No external circuitry required to correct for offsets
Independent red, green, and blue delay controls
Drives 4 double-terminated video loads
Digital and analog delay control
6-bit SPI bus
I2C bus
Analog voltage control
Fixed gain of 2
Low noise
High differential input impedance: 500 kΩ
32-lead, 5 mm × 5 mm LFCSP
APPLICATIONS
Keyboard-video-mouse (KVM)
Digital signage
RGB video over UTP cable
Professional video projection and distribution
HD video
Security video
General broadband delay lines
GENERAL DESCRIPTION
The AD8120 is a triple broadband skew-compensating delay line
that corrects for time mismatch between video signals incurred
by transmission in unshielded twisted pairs of Category 5 and
Category 6 type cables. Skew between the individual pairs exists
in most types of multipair UTP cables due to the different twist
rates that are used for each pair to minimize crosstalk between
pairs. For this reason, some pairs are longer than others, and in
long cables, the difference in propagation time between two pairs
can be well into the tens of nanoseconds.
The AD8120 contains three delay paths that provide broadband
delays up to 50 ns, in 0.8 ns increments, using 64 digital control
steps or analog control adjustment. The delay technique used in
the AD8120 minimizes noise and offset at the outputs.
The bandwidth of the AD8120 ranges from 150 MHz to 200 MHz,
depending on the delay setting. This wide bandwidth makes the
AD8120 ideal for use in applications that receive high resolution
video over UTP cables.
The logic circuitry of the AD8120 provides individual delay con-
trols for each channel. The delay times are set independently
using a standard 4-wire SPI bus or a standard I2C bus, or by
applying analog control voltages to the VCR, VCG, and VCB pins.
Analog control offers a simple solution for systems that do not
have digital control available.
The AD8120 is designed to be used with the AD8123 triple
UTP equalizer in video over UTP applications, but it can
also be used in other applications where similar controllable
broadband delays are required.
The AD8120 is available in a 5 mm × 5 mm, 32-lead LFCSP
and is rated to operate over the industrial temperature range
of −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
Rd
Gd
Bd
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2012 Analog Devices, Inc. All rights reserved.






AD8120 Datasheet, Funktion
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage
Internal Power Dissipation
32-Lead LFCSP at TA = 25°C
Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature
(Soldering 10 sec)
Junction Temperature
Rating
±6 V
3.5 W
VS− − 0.3 V to VS+ + 0.3 V
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, for a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
5 mm × 5 mm, 32-Lead LFCSP
θJA θJC Unit
36 2
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8120 package is
limited by its junction temperature. The maximum safe junction
temperature for plastic encapsulated devices, as determined by
the glass transition temperature of the plastic, is approximately
150°C. Temporarily exceeding this limit may cause a shift in the
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175°C for an extended period can result in device failure.
AD8120
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power dissipation is the voltage between the supply pins (VS+
and VS−) times the quiescent current (IS). Power dissipated due
to load drive depends upon the particular application. It is cal-
culated by multiplying the load current by the associated voltage
drop across the device. RMS voltages and currents must be used
in these calculations.
Airflow increases heat dissipation by reducing θJA.
To ensure optimal thermal performance, the exposed paddle
must be in an optimized thermal connection with an external
plane layer.
6
5
4
3
2
1
0
–40 –20
0
20 40 60
AMBIENT TEMPERATURE (°C)
80
Figure 2. Maximum Power Dissipation vs. Ambient Temperature
on a JEDEC Standard 4-Layer Board
ESD CAUTION
Rev. A | Page 5 of 16

6 Page









AD8120 pdf, datenblatt
Data Sheet
CS
SCK
AD8120
SDI 0 0 0 0 0 0 0 1 X X 1 0 1 0 1 0
SDO
XXXXXXXX XXXXXXXX
START
BYTE 1
R/W BIT AND COLOR REGISTER
BYTE 2
DATA
STOP
Figure 17. Setting the Green Register to Delay Code 42 Using SPI
CS
SCK
SDI 1 0 0 0 0 0 1 0 X X X X X X X X
SDO
XXXXXXX X XX0 1 0 1 0 1
START
BYTE 1
R/W BIT AND COLOR REGISTER
BYTE 2
DATA
STOP
Figure 18. Reading Delay Code 21 from the Blue Register Using SPI
Rev. A | Page 11 of 16

12 Page





SeitenGesamt 17 Seiten
PDF Download[ AD8120 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
AD812Dual/ Current Feedback Low Power Op AmpAnalog Devices
Analog Devices
AD8120Triple Skew-Compensating Video Delay LineAnalog Devices
Analog Devices
AD8122Triple Differential ReceiverAnalog Devices
Analog Devices
AD8123Triple Differential ReceiverAnalog Devices
Analog Devices
AD8124Triple Differential ReceiverAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche