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PDF AD7781 Data sheet ( Hoja de datos )
| Número de pieza | AD7781 | |
| Descripción | Low Power Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
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FEATURES
Pin-programmable filter response
Update rate: 10 Hz or 16.7 Hz
Pin-programmable in-amp gain
Pin-programmable power-down and reset
Status function
Internal clock oscillator
Internal bridge power-down switch
Current
115 μA typical (gain = 1)
330 μA typical (gain = 128)
Simultaneous 50 Hz/60 Hz rejection
Power supply: 2.7 V to 5.25 V
−40°C to +105°C temperature range
Independent interface power supply
Packages
14-lead, narrow body SOIC
16-lead TSSOP
2-wire serial interface (read-only device)
SPI compatible
Schmitt trigger on SCLK
APPLICATIONS
Weigh scales
Pressure measurement
Industrial process control
Portable instrumentation
www.DaGtaESNhEeeRt4AUL.cDomESCRIPTION
The AD7781 is a complete, low power front-end solution for
bridge sensor products, including weigh scales, strain gages,
and pressure sensors. It contains a precision, low power, 20-bit
sigma-delta (Σ-Δ) ADC, an on-chip, low noise programmable
gain amplifier (PGA), and an on-chip oscillator.
Consuming only 330 μA, the AD7781 is particularly suitable for
portable or battery-operated products where very low power is
required. The AD7781 also has a power-down mode that allows
the user to switch off the power to the bridge sensor and power
down the AD7781 when not converting, thus increasing the
battery life of the product.
For ease of use, all the features of the AD7781 are controlled by
dedicated pins. Each time that a data read occurs, eight status bits
are appended to the 20-bit conversion. These status bits contain a
pattern sequence that can be used to confirm the validity of the
serial transfer.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
20-Bit, Pin-Programmable,
Low Power Sigma-Delta ADC
AD7781
FUNCTIONAL BLOCK DIAGRAM
GND AVDD GAIN
REFIN(+) REFIN(–)
AIN(+)
AIN(–)
G=1
OR 128
20-BIT Σ-Δ
ADC
BPDSW
AD7781
INTERNAL
CLOCK
Figure 1.
DOUT/RDY
SCLK
DVDD
FILTER
PDRST
Table 1.
Parameter
Output Data Rate
RMS Noise
C Grade
B Grade
P-P Resolution
C Grade
B Grade
Settling Time
Gain = 128
10 Hz 16.7 Hz
44 nV
55 nV
65 nV
90 nV
17.6
17.3
300 ms
17.1
16.6
120 ms
Gain = 1
10 Hz 16.7 Hz
2.4 μV
2.4 μV
2.7 μV
2.7 μV
18.8
18.8
300 ms
18.7
18.7
120 ms
The on-chip PGA has a gain of 1 or 128, supporting a full-scale
differential input of ±5 V or ±39 mV. The device has two filter
response options. The filter response at the 16.7 Hz update rate
provides superior dynamic performance. The settling time is
120 ms at this update rate. At the 10 Hz update rate, the filter
response provides better than −45 dB of stop-band attenuation.
In load cell applications, this stop-band rejection is useful to
reject low frequency mechanical vibrations of the load cell. The
settling time is 300 ms at this update rate. Simultaneous 50 Hz/
60 Hz rejection occurs at both the 10 Hz and 16.7 Hz update rates.
The AD7781 operates with a power supply from 2.7 V to 5.25 V.
It is available in a narrow body, 14-lead SOIC package and in a
16-lead TSSOP package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
1 page  
AD7781
TIMING CHARACTERISTICS
AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.
Table 3.
Parameter1
Read2
t1
t2
t3 3
t4
Reset
t5
t6 5
Limit at TMIN, TMAX
100
100
0
60
80
10
130
100
120
300
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ms typ
ms typ
Test Conditions/Comments
SCLK high pulse width
SCLK low pulse width
SCLK active edge to data valid delay4
DVDD = 4.75 V to 5.25 V
DVDD = 2.7 V to 3.6 V
SCLK inactive edge to DOUT/RDY high
PDRST low pulse width
FILTER/GAIN change to data valid delay
Update rate = 16.7 Hz
Update rate = 10 Hz
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2 See Figure 3.
3 The values of t3 are measured using the load circuit of Figure 2 and are defined as the time required for the output to cross the VOL or VOH limits.
4 SCLK active edge is falling edge of SCLK.
5 The PDRST high to data valid delay is typically 1 ms longer than t6 because the internal oscillator requires time to power up and settle.
Circuit and Timing Diagrams
ISINK (1.6mA WITH DVDD = 5V,
100µA WITH DVDD = 3V)
TO
OUTPUT
PIN
50pF
1.6V
www.DataSheet4U.com
ISOURCE (200µA WITH DVDD = 5V,
100µA WITH DVDD = 3V)
Figure 2. Load Circuit for Timing Characterization
PDRST
(INPUT)
DOUT/RDY
(OUTPUT)
t5
Figure 4. Resetting the AD7781
DOUT/RDY
(OUTPUT)
SCLK
(INPUT)
MSB
t3
t1
LSB
t4
t2
Figure 3. Read Cycle Timing Diagram
GAIN OR FILTER
(INPUT)
DOUT/RDY
(OUTPUT)
t6
Figure 5. Changing Gain or Filter Option
Rev. 0 | Page 5 of 16
5 Page 
THEORY OF OPERATION
The AD7781 is a low power ADC that incorporates a precision,
20-bit, Σ-Δ modulator; a PGA; and an on-chip digital filter
intended for measuring wide dynamic range, low frequency
signals. The part provides a complete front-end solution for
bridge sensor applications such as weigh scales and pressure
sensors.
The device has an internal clock and one buffered differential
input. It offers a choice of two update rates (10 Hz or 16.7 Hz)
and two gain settings (1 or 128). These functions are controlled
using dedicated pins, which makes the interface easy to configure.
A 2-wire interface simplifies data retrieval from the AD7781.
FILTER, DATA RATE, AND SETTLING TIME
The AD7781 has two filter options. When the FILTER pin is
low, the 16.7 Hz filter is selected; when the FILTER pin is high,
the 10 Hz filter is selected. When the polarity of the FILTER pin
is changed, the AD7781 modulator and filter are reset immedi-
ately. DOUT/RDY is set high, and the ADC begins conversions
using the selected filter response. The first conversion requires
the total settling time of the filter. Subsequent conversions
occur at the selected update rate. The settling time of the 10 Hz
filter is 300 ms (three conversion cycles), and the settling time
of the 16.7 Hz filter is 120 ms (two conversion cycles).
When a step change occurs on the analog input, the AD7781
requires several conversion cycles to generate a valid conversion.
If the step change occurs synchronous to the conversion period, the
settling time of the AD7781 must be allowed to generate a valid
conversion. If the step change occurs asynchronous to the end
of a conversion, an extra conversion must be allowed to generate
a valid conversion. The data register is updated with all the con-
www.DavetarSsihoenest,4bUu.ct,ofmor an accurate result, the user must allow for the
required time.
Figure 20 and Figure 21 show the filter response for each filter.
The 10 Hz filter provides more than −45 dB of rejection in the
stop band. The only external filtering required on the analog
inputs is a simple R-C filter to provide rejection at multiples of
the master clock. A 1 kΩ resistor in series with each analog input,
a 0.01 μF capacitor from each input to GND, and a 0.1 μF
capacitor from AIN(+) to AIN(−) are recommended.
When the filter is changed, DOUT/RDY goes high and remains
high until the appropriate settling time for that filter elapses
(see Figure 5). Therefore, the user should complete any read
operations before changing the filter. Otherwise, 1s are read
back from the AD7781 because the DOUT/RDY pin is set high
following the filter change.
AD7781
0
–20
–40
–60
–80
–100
–120
0
20 40 60 80 100
INPUT SIGNAL FREQUENCY (Hz)
120
Figure 20. Filter Profile with Update Rate = 16.7 Hz (FILTER = 0)
0
–20
–40
–60
–80
–100
–120
0
20 40 60 80 100
INPUT SIGNAL FREQUENCY (Hz)
120
Figure 21. Filter Profile with Update Rate = 10 Hz (FILTER = 1)
GAIN
The AD7781 has two gain options: gain = 1 and gain = 128.
When the GAIN pin is low, the gain is set to 128; when the
GAIN pin is high, the gain is set to 1. The acceptable analog
input range is ±VREF/gain. Thus, with VREF = 5 V, the input range
is ±5 V when GAIN is high and ±39 mV when GAIN is low.
When the polarity of the GAIN pin is changed, the AD7781 modu-
lator and filter are reset immediately. DOUT/RDY is set high, and
the ADC begins conversions. DOUT/RDY remains high until
the appropriate settling time for the filter elapses (see Figure 5).
Therefore, the user should complete any read operations before
changing the gain. Otherwise, 1s are read back from the AD7781
because the DOUT/RDY pin is set high following the gain change.
The total settling time of the selected filter is required to generate
the first conversion after the gain change; subsequent conversions
occur at the selected update rate.
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD7781.PDF ] | |
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