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P89LPC952 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P89LPC952
Beschreibung (P89LPC952 / P89LPC954) 8-bit microcontroller
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
P89LPC952 Datasheet, Funktion
P89LPC952/954
8-bit microcontroller with accelerated two-clock 80C51 core
8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC
Rev. 04 — 24 July 2008
Product data sheet
1. General description
The P89LPC952/954 is a single-chip microcontroller, available in low cost packages,
based on a high performance processor architecture that executes instructions in two to
four clocks, six times the rate of standard 80C51 devices. Many system-level functions
have been incorporated into the P89LPC952/954 in order to reduce component count,
board space, and system cost.
2. Features
2.1 Principal features
I 8 kB/16 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte
pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
I 256-byte RAM data memory and a 256-byte auxiliary on-chip RAM.
I 8-input multiplexed 10-bit ADC with window comparator that can generate an interrupt
for in or out of range results. Two analog comparators with selectable inputs and
reference source.
I Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output) and a 23-bit system timer that can also be used
as a RTC.
I Two enhanced UARTs with a fractional baud rate generator, break detect, framing
error detection, and automatic address detection; 400 kHz byte-wide I2C-bus
communication port and SPI communication port.
I High-accuracy internal RC oscillator option, with clock doubler option, allows operation
without external oscillator components. The RC oscillator option is selectable and fine
tunable. Fast switching between the internal RC oscillator and any oscillator source
provides optimal support of minimal power active mode with fast switching to
maximum performance.
I 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
I 44-pin and 48-pin packages with 40 and 42 I/O pins minimum while using on-chip
oscillator and reset options.
I Port 5 has high current sourcing/sinking (20 mA) for all Port 5 pins. All other port pins
have high sinking capability (20 mA). A maximum limit is specified for the entire chip.
I Watchdog timer with separate on-chip oscillator, requiring no external components.
The watchdog prescaler is selectable from eight values.
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P89LPC952 Datasheet, Funktion
NXP Semiconductors
6. Pinning information
6.1 Pinning
P89LPC952/954
8-bit microcontroller with 10-bit ADC
P1.3/INT0/SDA 7
P1.2/T0/SCL 8
P1.1/RXD0 9
P1.0/TXD0 10
P3.1/XTAL1 11
P3.0/XTAL2/CLKOUT 12
VDD 13
P5.7 14
P5.6 15
P5.5 16
P5.4 17
P89LPC952FA
P89LPC954FA
39 P0.4/CIN1A/KBI4/AD03
38 P0.5/CMPREF/KBI5
37 P0.6/CMP1/KBI6
36 VDD
35 P0.7/T1/KBI7
34 P2.2/MOSI
33 P2.3/MISO
32 P2.4/SS
31 P2.5/SPICLK
30 P4.0
29 P4.1/TRIG
002aab307
Fig 3. PLCC44 pin configuration
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P89LPC952_954_4
Product data sheet
Rev. 04 — 24 July 2008
© NXP B.V. 2008. All rights reserved.
6 of 69

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P89LPC952 pdf, datenblatt
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
Table 3. Pin description …continued
Symbol
Pin
LQFP48 PLCC44
P2.5/SPICLK 27
31
P2.6
P2.7
P3.0 to P3.1
26
5
-
-
P3.0/XTAL2/
CLKOUT
7
12
P3.1/XTAL1 6
11
P4.0 to P4.7
P4.0
P4.1/TRIG
25
24
P4.2/TXD1
23
P4.3/RXD1
22
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30
29
28
27
LQFP44
25
-
-
6
5
24
23
22
21
Type Description
I/O P2.5 — Port 2 bit 5.
I/O SPICLK — SPI clock. When configured as master, this pin is
output; when configured as slave, this pin is input.
I/O P2.6 — Port 2 bit 6.
I/O P2.7 — Port 2 bit 7.
I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable
output type. During reset Port 3 latches are configured in the
input only mode with the internal pull-up disabled. The
operation of Port 3 pins as inputs and outputs depends upon
the port configuration selected. Each port pin is configured
independently. Refer to Section 7.13.1 “Port configurations”
and Table 11 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described
below:
I/O P3.0 — Port 3 bit 0.
O XTAL2 — Output from the oscillator amplifier (when a crystal
oscillator option is selected via the flash configuration.
O CLKOUT — CPU clock divided by 2 when enabled via SFR
bit (ENCLK -TRIM.6). It can be used if the CPU clock is the
internal RC oscillator, watchdog oscillator or external clock
input, except when XTAL1/XTAL2 are used to generate clock
source for the RTC/system timer.
I/O P3.1 — Port 3 bit 1.
I XTAL1 — Input to the oscillator circuit and internal clock
generator circuits (when selected via the flash configuration).
It can be a port pin if internal RC oscillator or watchdog
oscillator is used as the CPU clock source, and if
XTAL1/XTAL2 are not used to generate the clock for the
RTC/system timer.
I/O Port 4: Port 4 is an 8-bit I/O port with a user-configurable
output type. During reset Port 4 latches are configured in the
input only mode with the internal pull-up disabled. The
operation of Port 4 pins as inputs and outputs depends upon
the port configuration selected. Each port pin is configured
independently. Refer to Section 7.13.1 “Port configurations”
and Table 11 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 4 also provides various special functions as described
below:
I/O P4.0 — Port 4 bit 0.
I/O P4.1 — Port 4 bit 1.
O TRIG — Debugger trigger output.
I/O P4.2 — Port 4 bit 2.
O TXD1 — Transmitter output for serial port 1.
I/O P4.3 — Port 4 bit 3.
I RXD1 — Receiver input for serial port 1.
P89LPC952_954_4
Product data sheet
Rev. 04 — 24 July 2008
© NXP B.V. 2008. All rights reserved.
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