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PDF AS4DDR16M72PBG Data sheet ( Hoja de datos )
| Número de pieza | AS4DDR16M72PBG | |
| Descripción | 16Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit | |
| Fabricantes | Austin Semiconductor | |
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iPEM
1.2 Gb SDRAM-DDR
Austin Semiconductor, Inc. AS4DDR16M72PBG
16Mx72 DDR SDRAM
iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
DDR SDRAM Data Rate = 200, 250, 266, 333Mbps
Package:
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CLK and CLK#)
Commands entered on each positive CLK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/received
with data, i.e., source-synchronous data capture
(one per byte)
DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
Two data mask (DM) pins for masking write data
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Industrial, Enhanced and Military Temperature
Ranges
Organized as 16M x 72/80
Weight: AS4DDR16M72PBG = 3.50 grams typical
* This product and or it’s specifications is subject to change without notice..
BENEFITS
40% SPACE SAVINGS
Reduced part count
Reduced I/O count
•34% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 32M x 72 density
(AS4DDR32M72PBG)
Meets or exceeds published specifications of
White’s W3E16M72S-XBX
www.DataSheet4U.com
Monolithic Solution
Integrated MCP Solution
O 11.9 11.9 11.9 11.9 11.9
P
T
I
22.3
O
N
S
Area
I/O
Count
5 x 265mm2 = 1328mm2 Plus
5 x 66 pins = 320 pins
32
800mm2
219 Balls
S
A
V
25 I
N
G
S
40+%
34 %
AS4DDR16M72PBG
Rev. 2.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
iPEM
1.2 Gb SDRAM-DDR
Austin Semiconductor, Inc. AS4DDR16M72PBG
GENERAL DESCRIPTION
FUNCTIONAL DESCRIPTION
The 1.2Gb DDR SDRAM MCM, is a high-speed CMOS, Read and write accesses to the DDR SDRAM are burst oriented;
dynamic random-access, memory using 5 chips containing accesses start at a selected location and continue for a
268,435,456 bits. Each chip is internally configured as a programmed number of locations in a programmed sequence.
quad-bank DRAM. Each of the chip’s 67,108,864-bit banks Accesses begin with the registration of an ACTIVE command
is organized as 8,192 rows by 512 columns by 16 bits.
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
The 128MB(1.2Gb) DDR SDRAM MCM uses a DDR are used to select the bank and row to be accessed (BA0 and
architecture to achieve high-speed operation. The double BA1 select the bank, A0-12 select the row). The address bits
data rate architecture is essentially a 2n-prefetch architecture registered coincident with the READ or WRITE command are
with an interface designed to transfer two data words per used to select the starting column location for the burst access.
clock cycle at the I/O pins. A single read or write access for
the 128MB DDR SDRAM effectively consists of a single 2n- Prior to normal operation, the SDRAM must be initialized. The
bit wide, one-clock-cycle data tansfer at the internal DRAM following sections provide detailed information covering device
core and two corresponding n-bit wide, one-half-clock-cycle initialization, register defi nition, command descriptions and
data transfers at the I/O pins.
device operation.
A bidirectional data strobe (DQS) is transmitted externally, INITIALIZATION
along with data, for use in data capture at the receiver. DQS DDR SDRAMs must be powered up and initialized in a
is a strobe transmitted by the DDR SDRAM during READs predefined manner. Operational procedures other than those
and by the memory contoller during WRITEs. DQS is specified may result in undefined operation. Power must first
edgealigned with data for READs and center-aligned with be applied to VCC and VCCQ simultaneously, and then to VREF
data for WRITEs. Each chip has two data strobes, one for (and to the system VTT). VTT must be applied after VCCQ to avoid
the lower byte and one for the upper byte.
device latch-up, which may cause permanent damage to the
device. VREF can be applied any time after VCCQ but is expected
The 128MB DDR SDRAM operates from a differential clock to be nominally coincident with VTT. Except for CKE, inputs are
(CLK and CLK#); the crossing of CLK going HIGH and CLK# not recognized as valid until after VREF is applied. CKE is an
going LOW will be referred to as the positive edge of CLK. SSTL_2 input but will detect an LVCMOS LOW level after VCC is
Commands (address and control signals) are registered applied. Maintaining an LVCMOS LOW level on CKE during
at every positive edge of CLK. Input data is registered on powerup is required to ensure that the DQ and DQS outputs
both edges of DQS, and output data is referenced to both will be in the High-Z state, where they will remain until driven in
edges of DQS, as well as to both edges of CLK.
normal operation (by a read access). After all power supply and
reference voltages are stable, and the clock is stable, the DDR
Read and write accesses to the DDR SDRAM are burst SDRAM requires a 200µs delay prior to applying an executable
oriented; accesses start at a selected location and continue command.
www.DfaotarSaheperto4Ugr.caommmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE Once the 200µs delay has been satisfied, a DESELECT or
command, which is then followed by a READ or WRITE NOP command should be applied, and CKE should be brought
command. The address bits registered coincident with the HIGH. Following the NOP command, a PRECHARGE ALL
ACTIVE command are used to select the bank and row to be command should be applied. Next a LOAD MODE REGISTER
accessed. The address bits registered coincident with the command should be issued for the extended mode register
READ or WRITE command are used to select the bank and (BA1 LOW and BA0 HIGH) to enable the DLL, followed by another
the starting column location for the burst access.
LOAD MODE REGISTER command to the mode register (BA0/
BA1 both LOW) to reset the DLL and to program the operating
The DDR SDRAM provides for programmable READ or parameters. Two-hundred clock cycles are required between
WRITE burst lengths of 2, 4, or 8 locations. An auto precharge the DLL reset and any READ command. A PRECHARGE ALL
function may be enabled to provide a selftimed row command should then be applied, placing the device in the all
precharge that is initiated at the end of the burst access. banks idle state.
The pipelined, multibank architecture of DDR SDRAMs allows Once in the idle state, two AUTO REFRESH cycles must be
for concurrent operation, thereby providing high effective performed (tRFC must be satisfi ed.) Additionally, a LOAD MODE
bandwidth by hiding row precharge and activation time. REGISTER command for the mode register with the reset DLL
bit deactivated (i.e., to program operating parameters without
An auto refresh mode is provided, along with a powersaving resetting the DLL) is required. Following
power-down mode.
these requirements, the DDR SDRAM is ready for normal
operation.
AS4DDR16M72PBG
Rev. 2.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
iPEM
1.2 Gb SDRAM-DDR
Austin Semiconductor, Inc. AS4DDR16M72PBG
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on VCC, VCCQ Supply relative to VSS
Voltage on I/O pins relative to VSS
Operating Temperature TA (Mil)
Operating Temperature TA (Ind)
Storage Temperature, Plastic
Unit
-1 ot 3.6 V
-1 ot 3.6
-55 to +125
-40 to +85
-55 to +150
V
oC
oC
oC
Note: Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational conditions for extended periods may affect reliability.
CAPACITANCE (NOTE 13)
Parameter
Input Capacitance: CLK
Addresses, BA0-1 Input Capacitance
Input Capacitance: All other input-only pins
Input/Output Capacitance: I/O's
www.DataSheet4U.com
Symbol
C11
CA
C12
C10
Max
8
30
9
12
Unit
pF
pF
pF
pF
AS4DDR16M72PBG
Rev. 2.1 06/09
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
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