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EP9301 Schematic ( PDF Datasheet ) - Cirrus Logic

Teilenummer EP9301
Beschreibung Entry-level ARM9 System-on-chip Processor
Hersteller Cirrus Logic
Logo Cirrus Logic Logo 




Gesamt 30 Seiten
EP9301 Datasheet, Funktion
www.DataSheet4U.com
EP9301 Data Sheet
FEATURES
• 166-MHz ARM920T Processor
• 16-kbyte Instruction Cache
• 16-kbyte Data Cache
• Linux®, Microsoft® Windows® CE, enabled MMU
• 66-MHz System Bus
• MaverickKeyIDs
• 32-bit unique ID can be used for DRM-compliant,
128-bit random ID.
• Integrated Peripheral Interfaces
• 16-bit SDRAM Interface (up to 4 banks)
• 16-bit SRAM / FLASH / ROM
• Serial EEPROM Interface
• 1/10/100 Mbps Ethernet MAC
• Two UARTs
• Two-port USB 2.0 Full-speed Host (OHCI)
(12 Mbits per second)
• IrDA Interface
• ADC
• Serial Peripheral Interface (SPI) Port
• 6-channel Serial Audio Interface (I2S)
• 2-channel Low-cost Serial Audio Interface (AC'97)
Entry-level ARM9
System-on-chip Processor
• Internal Peripherals
• 12 Direct Memory Access (DMA) Channels
• Real-time Clock with software Trim
• Dual PLL controls all clock domains.
• Watchdog Timer
• Two General-purpose 16-bit Timers
• One General-purpose 32-bit Timer
• One 40-bit Debug Timer
• Interrupt Controller
• Boot ROM
• Package
• 208-pin LQFP
Serial
Audio
Interface
(2) UARTs
w/
IrDA
(2) USB
Hosts
Ethernet
MAC
12 Channel DMA
MaverickKeyTM
Processor Bus
Boot
ROM
Peripheral Bus
ARM920T
D-Cache I-Cache
16KB
16KB
MMU
Clocks &
Timers
Interrupts
& GPIO
Bus Bridge
SRAM &
Flash I/F
Unified
SDRAM I/F
MEMORY AND STORAGE
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
©Copyright 2005 Cirrus Logic (All Rights Reserved)
MAR ‘05
DS636PP5
1






EP9301 Datasheet, Funktion
EP9301
Entry Level ARM9 System-on-Chip Processor
www.DataSheet4U.com
Processor Core - ARM920T
The ARM920T is a Harvard architecture processor with
separate 16-kbyte instruction and data caches with an 8-
word line length but a unified memory. The processor
utilizes a five-stage pipeline consisting of fetch, decode,
execute, memory, and write stages. Key features include:
• ARM (32-bit) and Thumb (16-bit compressed)
instruction sets
• 32-bit Advanced Micro-Controller Bus Architecture
(AMBA)
• 16 kbyte Instruction Cache with lockdown
• 16 kbyte Data Cache (programmable write-through or
write-back) with lockdown
• MMU for Linux®, Microsoft® Windows® CE and other
operating systems
• Translation Look Aside Buffers with 64 Data and 64
Instruction Entries
• Programmable Page Sizes of 1 Mbyte, 64 kbyte,
4 kbyte, and 1 kbyte
• Independent lockdown of TLB Entries
MaverickKeyUnique ID
MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP9301 through the use of laser
probing technology. These IDs can then be used to
match secure copyrighted content with the ID of the
target device the EP9301 is powering, and then deliver
the copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for today’s
Internet appliances.
General Purpose Memory Interface (SDRAM,
SRAM, ROM, FLASH)
The EP9301 features a unified memory address model
where all memory devices are accessed over a common
address/data bus. Memory accesses are performed via
the Processor bus. The SRAM memory controller
supports 8- and 16-bit devices and accommodates an
internal boot ROM concurrently with 16-bit SDRAM
memory.
• 1 to 4 banks of 16-bit, 66 MHz SDRAM
• Address and data bus shared between SDRAM,
SRAM, ROM, and FLASH memory
• NOR FLASH memory supported
Table B. General Purpose Memory Interface Pin Assignments
Pin Mnemonic
Pin Description
SDCLK
SDCLKEN
SDCSn[3:0]
RASn
CASn
SDWEn
CSn[7:6] and CSn[3:0]
AD[25:0]
DA[15:0]
DQMn[1:0]
WRn
RDn
WAITn
SDRAM Clock
SDRAM Clock Enable
SDRAM Chip Selects 3-0
SDRAM RAS
SDRAM CAS
SDRAM Write Enable
Chip Selects 7, 6, 3, 2, 1, 0
Address Bus 25-0
Data Bus 15-0
SDRAM Output Enables / Data Masks
SRAM Write Strobe
SRAM Read / OE Strobe
SRAM Wait Input
6
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS636PP5

6 Page









EP9301 pdf, datenblatt
EP9301
Entry Level ARM9 System-on-Chip Processor
www.DataSheet4U.com
DC Characteristics
(TA = 0 to 70° C; CVDD = VDD_PLL = 1.8; RVDD = 3.3 V;
All grounds = 0 V; all voltages with respect to 0 V unless otherwise noted)
High level output voltage
Low level output voltage
High level input voltage
Low level input voltage
High level leakage current
Low level leakage current
Parameter
Iout = -4 mA
Iout = 4 mA
Vin = 3.3 V
Vin = 0
(Note 4)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
Symbol
Voh
Vol
Vih
Vil
Iih
Iil
Min Max
0.85 × RVDD
-
0.65 × RVDD
0.3
-
-
0.15 × RVDD
VDD + 0.3
0.35 × RVDD
10
- -10
Unit
V
V
V
V
µA
µA
Parameter
Power Supply Pins (Outputs Unloaded), 25° C
Power Supply Current:
CVDD / VDD_PLL Total
RVDD
Low-Power Mode Supply Current
CVDD / VDD_PLL Total
RVDD
Min Typ Max
- 180 230
- 45 80
- 2 3.5
- 1.0 2
Unit
mA
mA
mA
mA
Note:
4. For open drain pins, high level output voltage is dependent on the external load.
5. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation (See Table Q on
page 38). If an input is not driven, it should be tied to power or ground, depending on the particular function. If an I/O pin is not
driven and programmed as an input, it should be tied to power or ground through its own resistor.
12
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS636PP5

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