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P9NB50FP Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer P9NB50FP
Beschreibung STP9NB50FP
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 9 Seiten
P9NB50FP Datasheet, Funktion
www.DataSheet4U.com
STP9NB50
STP9NB50FP
N-CHANNEL 500V - 0.75 - 8.6 A TO-220/TO-220FP
PowerMeshMOSFET
TYPE
VDSS
RDS(on)
ID
STP9NB50
500 V < 0.85 8.6 A
STP9NB50FP
500 V < 0.85 4.9 A
s TYPICAL RDS(on) = 0.75
s EXTREMELY HIGH dv/dt CAPABILITY
s 100% AVALANCHE TESTED
s VERY LOW INTRINSIC CAPACITANCES
s GATE CHARGE MINIMIZED
DESCRIPTION
Using the latest high voltage MESH OVERLAY
process, STMicroelectronics has designed an ad-
vanced family of power MOSFETs with outstanding
performances. The new patent pending strip layout
coupled with the Company’s proprieraty edge termi-
nation structure, gives the lowest RDS(on) per area,
exceptional avalanche and dv/dt capabilities and
unrivalled gate charge and switching characteris-
tics.
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s SWITH MODE POWER SUPPLIES (SMPS)
s DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
3
2
1
TO-220
3
2
1
TO-220FP
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDS
VDGR
VGS
ID
ID
IDM (q)
PTOT
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 k)
Gate- source Voltage
Drain Current (continuos) at TC = 25°C
Drain Current (continuos) at TC = 100°C
Drain Current (pulsed)
Total Dissipation at TC = 25°C
Derating Factor
dv/dt (1) Peak Diode Recovery voltage slope
VISO
Insulation Withstand Voltage (DC)
Tstg Storage Temperature
Tj Max. Operating Junction Temperature
()Pulse width limited by safe operating area
May 2000
Value
STP9NB50 STP9NB50FP
500
500
±30
8.6
4.9
5.4 3.1
34.4 34.4
125 40
1 0.32
4.5 4.5
- 2000
–65 to 150
150
(1)ISD<9A, di/dt<200A/µ, VDD<V(BR)DSS,TJ<TJMAX
Unit
V
V
V
A
A
A
W
W/°C
V/ns
V
°C
°C
1/9






P9NB50FP Datasheet, Funktion
www.DataSheet4U.com
STP9NB50/FP
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/9

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