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PDF DS25CP104A Data sheet ( Hoja de datos )
| Número de pieza | DS25CP104A | |
| Descripción | (DS25CP104A / DS25CP114) 3.125 Gbps 4x4 LVDS Crosspoint Switch | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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DS25CP104A / DS25CP114
May 13, 2009
3.125 Gbps 4x4 LVDS Crosspoint Switch with Transmit
Pre-Emphasis and Receive Equalization
General Description
The DS25CP104A and DS25CP114 are 3.125 Gbps 4x4
LVDS crosspoint switches optimized for high-speed signal
routing and switching over lossy FR-4 printed circuit board
backplanes and balanced cables. Fully differential signal
paths ensure exceptional signal integrity and noise immunity.
The non-blocking architecture allows connections of any input
to any output or outputs. The switch configuration can be ac-
complished via external pins or the System Management Bus
(SMBus) interface.
The DS25CP104A and DS25CP114 feature four levels (Off,
Low, Medium, High) of transmit pre-emphasis (PE) and four
levels (Off, Low, Medium, High) of receive equalization (EQ)
settable via the SMBus interface. Off and Medium PE levels
and Off and Low EQ levels are settable with the external pins.
In addition, the SMBus circuitry enables the loss of signal
(LOS) monitors that can inform a system of the presence of
an open inputs condition (e.g. disconnected cable).
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. On the DS25CP104A each differential input and
output is internally terminated with a 100Ω resistor to lower
return losses, reduce component count and further minimize
board space. For added design flexibility the 100Ω input ter-
minations on the DS25CP114 have been eliminated. This
enables a designer to build custom crosspoint configurations
and distribution circuits that require a limited multidrop sig-
naling topology.
Features
■ DC - 3.125 Gbps low jitter, low skew, low power operation
■ Pin and SMBus configurable, fully differential, non-
blocking architecture
■ Pin (two levels) and SMBus (four levels) selectable pre-
emphasis and equalization eliminate ISI jitter
■ Wide Input Common Mode Range enables easy interface
to CML and LVPECL drivers
■ LOS circuitry detects open inputs fault condition
■ On-chip 100Ω input and output termination minimizes
insertion and return losses, reduces component count and
minimizes board space. The DS25CP114 eliminates the
on-chip input termination for added design flexibility.
■ 8 kV ESD on LVDS I/O pins protects adjoining
components
■ Small 6 mm x 6 mm LLP-40 space saving package
Applications
■ SD/HD/3G HD SDI Routers
■ OC-48 / STM-16
■ InfiniBand and FireWire
Typical Application
© 2009 National Semiconductor Corporation 300736
30073603
www.national.com
1 page  
wwPwi.nDatDaSehesect4Uri.cpomtions
Pin Name
IN0+, IN0- ,
IN1+, IN1-,
IN2+, IN2-,
IN3+, IN3-
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
EQ0, EQ1,
EQ2, EQ3
PE0, PE1,
PE2, PE3
EN_smb
Pin
Number
1, 2,
4, 5,
6, 7,
9, 10
29, 28,
27, 26,
24, 23,
22, 21
40, 39,
11, 12
31, 20,
19, 18
17
I/O, Type
I, LVDS
O, LVDS
I, LVCMOS
I, LVCMOS
I, LVCMOS
S00/SCL
S01/SDA
S10/ADDR0,
S11/ADDR1
S20/ADDR2,
S21/ADDR3
S30, S31
37 I, LVCMOS
36 I/O, LVCMOS
35, I, LVCMOS
34
33, I, LVCMOS
32
13, 14 I, LVCMOS
PWDN
38 I, LVCMOS
VDD
GND
3, 8, Power
15,25, 30
16, DAP Power
Pin Description
Inverting and non-inverting high speed LVDS input pins. These 4
input pairs have a 100 Ohm differential input termination on the
CP104A device. The CP114 eliminates the input termination for
added design flexibility.
Inverting and non-inverting high speed LVDS output pins. Each
output pair has an internal 100 Ohm termination to improve device
return loss characteristics.
Receive equalization level select pins. These pins are functional
regardless of the EN_smb pin state.
Transmit pre-emphasis level select pins. These pins are functional
regardless of the EN_smb pin state.
System Management Bus (SMBus) enable pin. The pin has an
internal pull down. When the pin is set to a [1], the device is in the
SMBus mode. All SMBus registers are reset when this pin is
toggled. There is a 20k pulldown device on this pin.
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT0.
In the SMBus mode, when the EN_smb = [1], these pins are
SMBus clock input and data input pins respectively.
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT1.
In the SMBus mode, when the EN_smb = [1], these pins are the
User-Set SMBus Slave Address inputs.
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT2.
In the SMBus mode, when the EN_smb = H, these pins are the
User-Set SMBus Slave Address inputs.
For EN_smb = [0], these pins select which LVDS input is routed
to the OUT3.
In the SMBus mode, when the EN_smb = [1], these pins are non-
functional and should be tied to either logic H or L.
For EN_smb = [0], this is the power down pin. When the PWDN is
set to a [0], the device is in the power down mode. The SMBus
circuitry can still be accessed provided the EN_smb pin is set to a
[1].
In the SMBus mode, the device is powered up by either setting the
PWDN pin to [1] OR by writing a [1] to the Control Register D[7]
bit ( SoftPWDN). The device will be powered down by setting the
PWDN pin to [0] AND by writing a [0] to the Control Register D[7]
bit ( SoftPWDN).
Power supply pins.
Ground pin and a pad (DAP - die attach pad).
Note: Center DAP connection must be made to GND for optimum electrical and thermal performance.
5 www.national.com
5 Page 
Symbol
Parameter
SwMwBwu.DsaAtaCShSePeEt4CUI.FcIoCmATIONS
fSMB SMBus Operating Frequency
tBUF Bus free time between Stop and Start
Conditions
tHD:SDA
Hold time after (Repeated) Start
Condition. After this period, the first clock
is generated.
tSU:SDA
tSU:SDO
tHD:DAT
tSU:DAT
tTIMEOUT
tLOW
tHIGH
tPOR
Repeated Start Condition setup time.
Stop Condition setup time
Data hold time
Data setup time
Detect clock low timeout
Clock low period
Clock high period
Time in which a device must be
operational after power-on reset
Conditions
Min Typ Max Units
10 100 kHz
4.7 μs
4.0 μs
4.7 μs
4.0 μs
300 ns
250 ns
25 35 ms
4.7 μs
4.0 50 μs
500 ms
Note 12: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 13: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 14: Specification is guaranteed by characterization and is not tested in production.
Note 15: tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
Note 16: tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode (any one input to
all outputs).
Note 17: tSKD3, Part to Part Skew, is defined as the difference between the same signal path of any two devices running at the same VCC and within 5°C of each
other within the operating temperature range.
Note 18: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Note 19: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted
algebraically.
Note 20: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
11 www.national.com
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| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet DS25CP104A.PDF ] | |
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