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AD9251 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9251
Beschreibung 1.8 V Dual Analog-to-Digital Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9251 Datasheet, Funktion
Data Sheet
14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
1.8 V Dual Analog-to-Digital Converter
AD9251
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
74.3 dBFS at 9.7 MHz input
71.5 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
33 mW per channel at 20 MSPS
73 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.45 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Hand held scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
FUNCTIONAL BLOCK DIAGRAM
AVDD
GND
SDIO SCLK CSB
VIN+A
VIN–A
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
REF
SELECT
SPI
ADC
PROGRAMMING DATA
AD9251
ADC
DIVIDE DUTY CYCLE
1 TO 8 STABILIZER
MODE
CONTROLS
ORA
D13A
D0A
DCOA
DRVDD
ORB
D13B
D0B
DCOB
CLK+ CLK–
SYNC
DCS
Figure 1.
PDWN DFS OEB
PRODUCT HIGHLIGHTS
1. The AD9251 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2. The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3. A standard serial port interface supports various product
features and functions, such as data output formatting,
internal clock divider, power-down, DCO/DATA timing
and offset adjustments, and voltage reference modes.
4. The AD9251 is packaged in a 64-lead RoHS compliant
LFCSP that is pin compatible with the AD9268 16-bit
ADC, the AD9258 14-bit ADC, the AD9231 12-bit ADC,
and the AD9204 10-bit ADC, enabling a simple migration
path between 10-bit and 16-bit converters sampling from
20 MSPS to 125 MSPS.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD9251 Datasheet, Funktion
Data Sheet
AD9251
AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
TWO-TONE SFDR
fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS)
CROSSTALK2
ANALOG INPUT BANDWIDTH
AD9251-20/AD9251-40
AD9251-65
AD9251-80
Temp Min Typ
Max Min Typ Max Min Typ Max Unit
25°C
25°C
Full 73.6
25°C
Full
25°C
74.7
74.4
73.7
71.5
74.5
74.3
73.6
73.7
71.5
74.3
74.1
73.6
72.5
71.5
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
25°C
Full 73.4
25°C
Full
25°C
74.6
74.3
73.6
70.0
74.4
74.2
73.4
73.6
70.0
74.1
74.0
73.5
72.4
70.0
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C 12.0
25°C 12.0
25°C 11.9
25°C 11.3
12.0 12.0 Bits
12.0 12.0 Bits
11.9 11.9 Bits
11.3 11.3 Bits
25°C −95
−95 −93 dBc
25°C −95
−95 −93 dBc
Full −81 −81
dBc
25°C −94
−94 −92 dBc
Full −81 dBc
25°C −80
−80 −80 dBc
25°C
25°C
Full 81
25°C
Full
25°C
95
94
93
80
95
94
81
93
80
93
93
92
81
80
dBc
dBc
dBc
dBc
dBc
dBc
25°C −98
−98 −97 dBc
25°C −98
−98 −97 dBc
Full −90 −90
dBc
25°C −98
−98 −96 dBc
Full −89 dBc
25°C −95
−95 −95 dBc
25°C 90
Full −110
25°C 700
90
−110
700
90
−110
700
dBc
dBc
MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
Rev. B | Page 5 of 36

6 Page









AD9251 pdf, datenblatt
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9251
CLK+ 1
CLK– 2
SYNC 3
NC 4
NC 5
(LSB) D0B 6
D1B 7
D2B 8
D3B 9
DRVDD 10
D4B 11
D5B 12
D6B 13
D7B 14
D8B 15
D9B 16
PIN 1
INDICATOR
AD9251
TOP VIEW
(Not to Scale)
48 PDWN
47 OEB
46 CSB
45 SCLK/DFS
44 SDIO/DCS
43 ORA
42 D13A (MSB)
41 D12A
40 D11A
39 D10A
38 D9A
37 DRVDD
36 D8A
35 D7A
34 D6A
33 D5A
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND
TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL
STRENGTH BENEFITS.
Figure 5. Pin Configuration
Table 8. Pin Function Description
Pin No.
Mnemonic
0 GND
1, 2 CLK+, CLK−
3 SYNC
4, 5, 25, 26
NC
6 to 9, 11 to 18, 20, 21
D0B to D13B
10, 19, 28, 37
DRVDD
22 ORB
23 DCOB
24 DCOA
27, 29 to 36, 38 to 42
D0A to D13A
43 ORA
44 SDIO/DCS
45 SCLK/DFS
46 CSB
47 OEB
48 PDWN
49, 50, 53, 54, 59, 60, 63, 64 AVDD
51, 52
VIN+A, VIN−A
Description
Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND.
Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.
Do Not Connect.
Channel B Digital Outputs. D13B = MSB.
Digital Output Driver Supply (1.8 V to 3.3 V).
Channel B Out-of-Range Digital Output.
Channel B Data Clock Digital Output.
Channel A Data Clock Digital Output.
Channel A Digital Outputs. D13A = MSB.
Channel A Out-of-Range Digital Output.
SPI Data Input/Output (SDIO). Bidirectional SPI Data I/O in SPI mode. 30 kΩ internal pull-
down in SPI mode.
Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode.
30 kΩ internal pull-up in non-SPI (DCS) mode.
SPI Clock (SCLK) Input in SPI mode. 30 kΩ internal pull-down.
Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal
pull-down.
DFS high = twos complement output.
DFS low = offset binary output.
SPI Chip Select. Active low enable; 30 kΩ internal pull-up.
Digital Input. Enable Channel A and Channel B digital outputs if low, tristate outputs if high.
30 kΩ internal pull-down.
Digital Input. 30 kΩ internal pull-down.
PDWN high = power-down device.
PDWN low = run device, normal operation.
1.8 V Analog Supply Pins.
Channel A Analog Inputs.
Rev. A | Page 11 of 36

12 Page





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