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CH7303 Schematic ( PDF Datasheet ) - Chrontel

Teilenummer CH7303
Beschreibung Chrontel CH7303 HDTV / DVI Encoder
Hersteller Chrontel
Logo Chrontel Logo 




Gesamt 15 Seiten
CH7303 Datasheet, Funktion
Chrontelwww.DataSheet4U.com
CH7303
Preliminary Advanced Information
Chrontel CH7303 HDTV / DVI Encoder
Features
General Description
• Digital Visual Interface (DVI) Transmitter up to 165M The CH7303 is a Display Controller device which accepts a
pixels/second
• DVI low jitter PLL
• DVI hot plug detection
• Analog YPrPb outputs for HDTV
• HDTV support for 480p, 576p, 720p, 1080i and 1080p
• MacrovisionTM copy protection support for HDTV
digital graphics input signal, and encodes and transmits data
through a DVI link (DFP can also be supported), VGA ports
(analog RGB) or a HDTV port (YPrPb). The device is able to
encode the video signals and generate synchronization signals
for analog HDTV interface standards and graphics standards
up to UXGA. The device accepts data over one 15-bit wide
variable voltage data port which supports 9 different data
• Programmable digital input interface supporting RGB formats including RGB and YCrCb.
(15, 16, 24 or 30 bit) and YCrCb input data formats
• Can output either RGB or YPrPb
• TV / Monitor connection detect
• Programmable power management
• Three 10-bit video DAC outputs
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Low voltage interface support to graphics device
The DVI processor includes a low jitter PLL for
generation of the high frequency serialized clock, and all
circuitry required to encode, serialize and transmit data.
The CH7303 is able to drive a DFP display at a pixel rate
of up to 165MHz, supporting UXGA resolution displays.
No scaling of input data is performed on the data output
to the DVI device.
• Offered in a 64-pin LQFP package
• Backward pin compatible with CH7301 or CH7009/11
• Support three additional 15 bit multiplexed RGB Input
In addition to DVI encoder modes, bypass modes are included
which perform color space conversion to HDTV standards
and generate and insert HDTV sync signals, or output VGA
Data Format (IDF 6,7.8)
style analog RGB for use as a CRT DAC.
† Patent number 5,781,241
¥ Patent number 5,914,753
Note: Other names and brands may be claimed as property by others.
HPDET
GPIO[1:0]
AS
SPC
SPD
RESET*
H,V
DE
VREF
2
XCLK,XCLK* 2
D[14:0] 15
ISET
Serial
Port
Control
H,V,DE
Latch
/
2
/
24
Clock
Driver
Data
Latch, /
Demux 30
Color Space
/ Conversion
24 Sync Decode
/
30
DVI Encode
DVI PLL
DVI
Serialize
DVI Driver
/ TLC, TLC*
2
/ TDC0, TDC0*
2
/
TDC1, TDC1*
2
/
TDC2, TDC2*
2
/
HSYNC,
2 VSYNC
HDTV
YPbPr
RGB
MUX
DAC 2
DAC 1
DAC 0
Three
10-bit DAC's
DAC[2]
DAC[1]
DAC[0]
Figure 1: Functional Block Diagram
209-0000-031 Rev. 0.4, 8/26/2002
1






CH7303 Datasheet, Funktion
CHRONTELwww.DataSheet4U.com
Table 4: EDTV Bypass
Active
Total
Resolution Resolution
720x480
858x525
720x483
858x525
720x480
856x525
720x483
856x525
720x576
864x625
Scan Type
Non-Interlaced
Non-Interlaced
Non-Interlaced
Non-Interlaced
Non-interlaced
Pixel Clock
(MHz)
27.0
27.027
26.937
26.964
27.0
CH7303
Frame Rate
(Hz)
60/1.001
60
60/1.001
60
50
Standard
EIA-770.2-A
SMPTE 293M
ITU-R BT.1358
2.1.2
RGB Bypass
In RGB Bypass mode, data, sync and clock signals are input to the CH7303 from a graphics device, and bypassed
directly to the D/A converters to implement a second CRT DAC function. External sync signals must be supplied from
the graphics device. These sync signals are buffered internally, and can be output to drive the CRT. The input data
format must be RGB in this operating mode. Input data is 2X multiplexed, and the XCLK clock signal can be 1X or 2X
times the pixel rate. The CH7303 can support a pixel rate of 165MHz. This operating mode uses all 8 bits of the DAC’s
10-bit range, and provides a nominal signal swing of 0.661V (or 0.7V depending on DAC Gain setting in control
registers) when driving a 75doubly terminated load. No scaling, scan conversion or flicker filtering is applied in
Bypass modes.
2.2 DVI Output
2.2.1
DVI Transmitter
In DVI Output mode, multiplexed input data, sync and clock signals are input to the CH7303 from the graphics
controller’s digital output port. Data will be 2X multiplexed, and the clock inputs can be 1X or 2X times the pixel rate.
Some examples of modes supported are shown in the table. For the table below, clock frequencies for given modes were
taken from VESA DISPLAY MONITOR TIMING SPECIFICATIONS if they were detailed there, not VESA TIMING
DEFINITION FOR FLAT PANEL MONITORS. The device is not dependent upon this set of timing specifications.
Any values of pixels/line, lines/frame and clock rate are acceptable, as long as the pixel rate remains below 165MHz.
The input format can be any RGB format or YCrCb (see Input Data Formats section).
Table 9: DVI Output
Graphics Active Aspect
Resolution
Ratio
Pixel Aspect
Ratio
720x400 4:3 1.35:1.00
640x400
8:5
1:1
640x480
4:3
1:1
720x480
4:3
9:8
720x576
4:3
15:12
800x600
4:3
1:1
1024x768
4:3
1:1
1280x720
16:9
1:1
Refresh Rate
(Hz)
<85
<85
<85
59.94
50
<85
<85
<60
XCLK
Frequency
(MHz)
<35.5
<31.5
<36
27
27
<57
<95
<67
DVI
Frequency
(MHz)
<355
<315
<360
270
270
<570
<950
<670
2.3 Input Interface
2.3.1
Overview
Two distinct methods of transferring data to the CH7303 are described. They are:
Multiplexed data, clock input at 1X the pixel rate
Multiplexed data, clock input at 2X the pixel rate
For the multiplexed data, clock at 1X pixel rate, the data applied to the CH7303 is latched with both edges of the clock
(also referred to as dual edge transfer mode or DDR). For the multiplexed data, clock at 2X pixel rate the data applied to
the CH7303 is latched with one edge of the clock (also known as single edge transfer mode or SDR). The polarity of the
pixel clock can be reversed under serial port control. In single edge transfer modes, the clock edge used to latch data is
programmable. In dual edge transfer modes, the clock edge used to latch the first half of each pixel is programmable.
6 209-0000-031 Rev. 0.4, 8/26/2002

6 Page









CH7303 pdf, datenblatt
CHRONTELwww.DataSheet4U.com
CH7303
Note :
VDATA - refers to all digital data (D[14:0]), clock (XCLK, XCLK*), sync (H, V) and DE inputs. VMISC - refers to GPIOx, RESET*, AS and
HPDET inputs and GPIOx, VSYNC and HSYNC outputs.
3.5 AC Specifications
Symbol
Description
Test Condition Min Typ Max Unit
fXCLK
tPIXEL
DCXCLK
tXJIT
tDVIR
tDVIF
tSKDIFF
Input (XCLK) frequency
Pixel time period
Input (XCLK) Duty Cycle
XCLK clock jitter tolerance
DVI Output Rise Time
(20% - 80%)
DVI Output Fall Time
(20% - 80%)
DVI Output intra-pair skew
TS + TH < 1.2ns
fXCLK = 75MHz
fXCLK = 165MHz
fXCLK = 165MHz
fXCLK = 165MHz
25 165 MHz
6.06 40 ns
30 70 %
2 ns
75 242 ps
75 242 ps
90 ps
tSKCC
DVI Output inter-pair skew
fXCLK = 165MHz
1.2 ns
tDVIJIT
TS
DVI Output Clock Jitter
Setup Time: D[11:0], H, V and
DE to XCLK, XCLK*
fXCLK = 165MHz
XCLK = XCLK* to
D[11:0], H, V, DE =
Vref
TBD
150 ps
ns
TH Hold Time: D[11:0], H, V and D[11:0], H, V, DE = TBD
DE to XCLK, XCLK*
Vref to XCLK =
XCLK*
ns
tSTEP
De-skew time increment
50 80 ps
12 209-0000-031 Rev. 0.4, 8/26/2002

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