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PDF AD5750 Data sheet ( Hoja de datos )
| Número de pieza | AD5750 | |
| Descripción | Industrial Current/Voltage Output Driver | |
| Fabricantes | Analog Devices | |
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Data Sheet
Industrial Current/Voltage Output Driver
with Programmable Ranges
AD5750/AD5750-1/AD5750-2
FEATURES
Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, 0 mA
to 24 mA, ±20 mA, and ±24 mA
±0.03% full-scale range (FSR) total unadjusted error (TUE)
±5 ppm/°C typical output drift
Voltage output ranges: 0 V to 5 V, 0 V to 10 V, ±5 V, and ±10 V
with 20% overrange
±0.02% FSR TUE
±3 ppm/°C typical output drift
Flexible serial digital interface
On-chip output fault detection
Packet error checking (PEC)
Asynchronous CLEAR function
Flexible power-up condition to 0 V or tristate
Power supply range
AVDD: +12 V (± 10%) to +24 V (± 10%)
AVSS: −12 V (± 10%) to −24 V (± 10%)
Output loop compliance to AVDD − 2.75 V
Temperature range: −40°C to +105°C
32-lead, 5 mm × 5 mm LFCSP package
APPLICATIONS
Process controls
Actuator controls
PLCs
GENERAL DESCRIPTION
The AD5750/AD5750-1/AD5750-2 are single-channel, low cost,
precision voltage/current output drivers with hardware- or
software-programmable output ranges. The software ranges are
configured via an SPI-/MICROWIRE™-compatible serial interface.
The AD5750/AD5750-1/AD5750-2 target applications in PLC
and industrial process control. The analog input to the AD5750/
AD5750-1/AD5750-2 is provided from a low voltage, single-supply
digital-to-analog converter (DAC) and is internally conditioned
to provide the desired output current/voltage range. Analog input
ranges available are 0 V to 2.5 V (AD5750-1/AD5750-2) or 0 V
to 4.096 V (AD5750).
The output current range is programmable across five current
ranges: 4 mA to 20 mA, 0 mA to 20 mA, 0 mA to 24 mA, ±20 mA,
and ±24 mA. An overrange of 2% is available on the unipolar
current ranges.
Voltage output is provided from a separate pin that can be
configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V
output ranges. An overrange of 20% is available on the voltage
ranges.
Analog outputs are short-circuit and open-circuit protected and
can drive capacitive loads of 1 µF and inductive loads of 0.1 H.
The devices are specified to operate with a power supply range
from ±12 V to ±24 V. Output loop compliance is 0 V to AVDD −
2.75 V.
The flexible serial interface is SPI and MICROWIRE compatible
and can operate in 3-wire mode to minimize the digital isolation
required in isolated applications. The interface also features an
optional PEC feature using CRC-8 error checking, useful in
industrial environments where data communication corruption
can occur.
The devices also include a power-on-reset function, ensuring that
the devices power up in a known state (0 V or tristate), and an
asynchronous CLEAR pin that sets the outputs to a zero scale/mid-
scale voltage output or the low end of the selected current range.
The HW SELECT pin is used to configure the parts for hardware
or software mode on power-up.
Table 1. Related Devices
Part Number Description
AD5422
Single channel, 16-bit, serial input current
source and voltage output DAC
AD5751
Industrial I/V output driver, single supply, 55 V
maximum supply, programmable ranges
AD5420
Single channel, 16-bit, serial input, 4 mA to
20 mA current source DAC
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
Parameter1
Zero-Scale Error Temperature
Coefficient3
Zero-Scale/Offset Error
Offset Error Temperature Coefficient3
Gain Error
Min
−5
−4
−3
−2.2
−0.05
−0.07
−0.04
Gain Error Temperature Coefficient3
Full-Scale Error
−0.05
Full-Scale Error Temperature
Coefficient3
VOLTAGE OUTPUT CHARACTERISTICS3
Headroom
Short-Circuit Current
Load
Capacitive Load Stability
RLOAD = ∞
RLOAD = 2 kΩ
RLOAD = ∞
−0.04
−0.07
1
DC Output Impedance
Leakage Current
0 V to 5 V Range, ¼ to ¾ Step
0 V to 5 V Range, 40 mV Input Step
Slew Rate
Output Noise
Output Noise Spectral Density
AC PSRR
DC PSRR
CURRENT OUTPUT
Output Current Ranges
Output Current Overranges
−110
0
0
4
−20
−24
0
0
4
Typ
±1
±0.5
±0.3
±2
±0.015
±0.5
±0.015
±1.5
Max
+5
+4
+3
+2.2
+0.05
+0.07
+0.04
+0.05
+0.04
+0.07
1.3
15
1
1
2
0.12
+110
7
4.5
2
2.5
45.5
165
−65
10
24
20
20
+20
+24
24.5
20.4
20.4
AD5750/AD5750-1/AD5750-2
Unit Test Conditions/Comments
ppm FSR/°C All bipolar ranges
mV
mV
mV
mV
ppm FSR/°C
% FSR
% FSR
% FSR
ppm FSR/°C
% FSR
% FSR
% FSR
ppm FSR/°C
0 V to 10 V range
TA = 25°C, 0 V to 10 V range
0 V to 5 V range
TA = 25°C, 0 V to 5 V range
All unipolar ranges
All bipolar/unipolar ranges,
AD5750 and AD5750-1
AD5750-2
TA = 25°C, AD5750, AD5750-1, and
AD5750-2
All bipolar/unipolar ranges,
AD5750 and AD5750-1
TA = 25°C, AD5750 and AD5750-1
AD5750-2
V
mA
kΩ
nF
nF
µF
Ω
nA
µs
µs
V/µs
µV rms
µV rms
nV/√Hz
dB
µV/V
mA
mA
mA
mA
mA
mA
mA
mA
Output unloaded
TA = 25°C
External compensation capacitor
required; see the Driving Inductive
Loads section
Output disabled; leakage to ground
Specified with 2 kΩ || 220 pF, ±0.05%
Specified with 2 kΩ || 220 pF, ±0.05%
Specified with 2 kΩ || 220 pF
0.1 Hz to 10 Hz bandwidth
100 kHz bandwidth
Measured at 10 kHz; specified with
2 kΩ || 220 pF
200 mV, 50 Hz/60 Hz sine wave super-
imposed on power supply voltage
Outputs unloaded
See the Detailed Description of
Features section
See the Detailed Description of
Features section
See the Detailed Description of
Features section
Rev. F | Page 5 of 36
5 Page 
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5750/AD5750-1/AD5750-2
SDO/VFAULT 1
CLRSEL 2
CLEAR 3
DVCC 4
GND 5
SYNC/RSET 6
SCLK/OUTEN 7
SDIN/R0 8
AD5750/
AD5750-1/
AD5750-2
TOP VIEW
(Not to Scale)
24 VSENSE+
23 VOUT
22 VSENSE–
21 AVSS
20 COMP1
19 COMP2
18 IOUT
17 AVDD
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE IS TIED TO AVSS.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 SDO/VFAULT Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in
readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. This pin
is a CMOS output.
Short-Circuit Fault Alert (VFAULT). In hardware mode, this pin acts as a short-circuit fault alert pin and is
asserted low when a short-circuit error is detected. This pin is an open-drain output and must be connected to
a pull-up resistor.
2
CLRSEL
In hardware or software mode, this pin selects the clear value, either zero-scale or midscale code. In software
mode, this pin is implemented as a logic OR with the internal CLRSEL bit.
3
CLEAR
Active High Input. Asserting this pin sets the output current/voltage to zero-scale code or midscale code of the
range selected (user selectable). CLEAR is a logic OR with the internal clear bit.
In software mode, during power-up, the CLEAR pin level determines the power-on condition of the voltage
channel, which can be active 0 V or tristate. See the Asynchronous Clear (CLEAR) section for more details.
4 DVCC
Digital Power Supply.
5 GND
Ground Connection.
6 SYNC/RSET Positive Edge Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift register data
into the AD5750/AD5750-1/AD5750-2, also updating the output.
Resistor Select (RSET). In hardware mode, this pin selects whether the internal or the external current sense resistor is
used. If RSET = 0, the external sense resistor is chosen, and if RSET = 1, the internal sense resistor is chosen.
7 SCLK/OUTEN Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling edge of
SCLK. This pin operates at clock speeds up to 50 MHz.
Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin.
8
SDIN/R0
Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK.
Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output
current/voltage range setting on the part.
9
AD2/R1
Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD1 and AD0, allows up to eight
devices to be addressed on one bus.
Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output
current/voltage range setting on the part.
10
AD1/R2
Device Addressing Bit (AD1). In software mode, this pin, in conjunction with AD2 and AD0, allows up to eight
devices to be addressed on one bus.
Range Decode Bit (R2). In hardware mode, this pin, in conjunction with R0, R1, and R3, selects the output
current/voltage range setting on the part.
Rev. F | Page 11 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD5750.PDF ] | |
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