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AD5734R Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5734R
Beschreibung (AD57x4R) Unipolar/Bipolar Voltage Output DACs
Hersteller Analog Devices
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Gesamt 30 Seiten
AD5734R Datasheet, Funktion
www.DataSheet4U.com
Preliminary Technical Data
Complete, Quad, 12-/14-/16-Bit, Serial Input,
Unipolar/Bipolar Voltage Output DACs
AD5724R/AD5734R/AD5754R
FEATURES
Complete, quad, 12-/14-/16-bit D/A converter
Operates from single/dual supplies
Software programmable output range
+5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V
INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum
Total unadjusted error (TUE): 0.1% FSR maximum
Settling time: 10 µs maximum
Integrated reference: 5 ppm/°C typ.
Integrated reference buffers
Output control during power-up/brownout
Simultaneous updating via LDAC
Asynchronous CLR to zero-/mid-scale
DSP/microcontroller-compatible serial interface
24-lead TSSOP
Operating temperature range: −40°C to +85°C
iCMOS™ process technology1
APPLICATIONS
Industrial automation
Closed-loop servo control, process control
Automotive test and measurement
Programmable logic controllers
GENERAL DESCRIPTION
The AD5724R/AD5734R/AD5754R are quad, 12-/14-/16-bit
serial input, voltage output, digital-to-analog converters. They
operate from single supply voltages of +4.5 V up to +16.5 V or
dual supply voltages from ±4.5 V up to ±16.5 V. Nominal full-
scale output range is software-selectable from the options of
+5 V, +10 V, +10.8 V, ±5 V, ±10 V, or ±10.8 V. Integrated output
amplifiers, reference buffers, and proprietary power-up/power-
down control circuitry are also provided.
The parts offer guaranteed monotonicity, integral nonlinearity
(INL) of ±16 LSB maximum, low noise, 10 µs maximum settling
time, and an on-chip +2.5 V reference.
The AD5724R/AD5734R/AD5754R use a serial interface that
operates at clock rates up to 30 MHz and are compatible with
DSP and microcontroller interface standards. Double buffering
allows the simultaneous updating of all DACs. The input coding
is user-selectable twos complement or offset binary for a bipolar
output (depending on the state of pin BIN/2sComp), and
straight binary for a unipolar output. The asynchronous clear
function clears all DAC registers to a user-selectable zero-scale
or mid-scale output. The parts are available in a 24-lead TSSOP
and offer guaranteed specifications over the −40°C to +85°C
industrial temperature range.
Table 1. Pin Compatible Devices
Part Number
Description
AD5724/AD5734/AD5754
AD5724R/AD5734R/AD5754R
without internal reference.
AD5722/AD5732/AD5752
Complete, dual, 12-/14-/16-bit,
serial input, unipolar/bipolar,
voltage output DAC.
AD5722R/AD5732R/AD5752R AD5722/AD5732/AD5752 with
internal reference.
1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology
platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and
package size, and increased AC and DC performance.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.






AD5734R Datasheet, Funktion
wwAwD.D5at7aS2h4eeRt4/UA.coDm5734R/AD5754R
Preliminary Technical Data
SINGLE SUPPLY SPECIFICATIONS
AVDD = 4.5 V1 to 16.5 V, AVSS = 0 V, GND = 0 V, REFIN= 2.5 V external, DVCC = 2.7 V to 5.5 V,
RLOAD = 2 kΩ, CLOAD = 200 pF; all specifications TMIN to TMAX, 10 V range unless otherwise noted.
Table 3.
Parameter
ACCURACY
Resolution
AD5754R
AD5734R
AD5724R
Total Unadjusted Error (TUE)
Relative Accuracy (INL)
B Grade
Differential Nonlinearity (DNL)
Zero-Scale Error
Zero-Scale TC2
Offset Error
Gain Error
Gain TC2
DC Crosstalk2
REFERENCE INPUT/OUTPUT
Reference Input2
Reference Input Voltage
DC Input Impedance
Input Current
Reference Range
Reference Output
Output Voltage
Reference TC
Output Noise (0.1 Hz to 10 Hz)2
Noise Spectral Density2
Output Drift vs. Time2
OUTPUT CHARACTERISTICS2
Output Voltage Range
Headroom
Output Voltage TC
Output Voltage Drift vs. Time
Short Circuit Current
Load
Capacitive Load Stability
DC Output Impedance
DIGITAL INPUTS2
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
Pin Capacitance
DIGITAL OUTPUTS (SDO)2
VOL, Output Low Voltage
Value
16
14
12
0.1
±16
±1
+10
±4
±10
±0.02
±8
0.6
Unit Test Conditions/Comments
Outputs unloaded
Bits
Bits
Bits
% FSR max
Across temperature and supplies
LSB max
LSB max
mV max
ppm FSR/°C max
mV max
% FSR max
ppm FSR/°C max
LSB max
@ 16-bit resolution
Guaranteed monotonic (@ 16-bit resolution)
@ 25°C, error at other temperatures obtained using Zero-Scale
TC
@ 25°C, error at other temperatures obtained using Gain TC
@ 16-bit resolution
2.5
1
±10
2 to 3
V nom
MΩ min
µA max
V min to max
±1% for specified performance
Typically 100 MΩ
Typically ±30 nA
2.498 to 2.502
±5
18
75
±40
±50
V min to V max
ppm/°C max
µV p-p typ
nV/√Hz typ
ppm/500 hr typ
ppm/1000 hr typ
@ 25°C
@ 10 kHz
10.8
12
0.9
0.5
±8
±12
±15
20
2
4000
0.5
2
0.8
±1
5
V max
V max
V max
V typ
ppm FSR/°C max
ppm/500 hr typ
ppm/1000 hr typ
mA typ
KΩ min
pF max
Ω typ
V min
V max
µA max
pF max
AVDD = 11.7 V min, REFIN = 2.5 V
AVDD = 12.9 V min, REFIN = 3.75 V
For specified performance
DVCC = 2.7 V to 5.5 V, JEDEC compliant
Per pin
Per pin
0.4 V max DVCC = 5 V ± 10%, sinking 200 µA
Rev. PrC | Page 6 of 32

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AD5734R pdf, datenblatt
wwPwr.DealtaimSheient4aUr.cyomTechnical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5724R/AD5734R/AD5754R
AVSS 1
24 AVDD
NC 2
23 VOUTC
VOUTA
3
AD5724R/
AD5734R/
22 VOUTD
VOUTB 4 AD5754R 21 SIG_GND
BIN/2sCOMP 5
20 SIG_GND
TOP VIEW
NC 6 (Not to Scale) 19 DAC_GND
SYNC 7
18 DAC_GND
SCLK 8
17 REFIN/REFOUT
SDIN 9
16 SDO
LDAC 10
15 GND
CLR 11
14 DVCC
NC 12
13 NC
NC = NO CONNECT
Figure 5.Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic
Description
1 AVSS
Negative Analog Supply Pin. Voltage ranges from –4.5 V to –16.5 V. This pin can be connected to 0 V if output
ranges are unipolar.
2, 6, 12, 13 NC
Do not connect to these pins.
3 VOUTA Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
4 VOUTB Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
5 BIN/2sCOMP Determines the DAC coding for a bipolar output range. This pin should be hardwired to either DVCC or GND.
When hardwired to DVCC, input coding is offset binary. When hardwired to GND, input coding is twos
complement. (For unipolar output ranges, coding is always straight binary).
7 SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred on the falling edge of SCLK.
8 SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock
speeds up to 30 MHz.
9 SDIN
Serial Data Input. Data must be valid on the falling edge of SCLK.
10 LDAC
Load DAC, Logic Input. This is used to update the DAC registers and consequently, the analog output. When
tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high
during the write cycle, the DAC input register is updated, but the output update is held off until the falling
edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC.
The LDAC pin should not be left unconnected.
11 CLR1
Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or mid-scale code (user-selectable).
14 DVCC
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
15 GND
Ground Reference Pin.
16 SDO
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is
clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
17 REFIN/REFOUT External Reference Voltage Input and Internal Reference Voltage Output. Reference input range is 2 V to 3 V.
REFIN = 2.5 V for specified performance. REFOUT = 2.5 V ± 2 mV @ 25°C.
18, 19
DAC_GND
Ground reference pins for the four digital-to-analog converters.
20, 21
SIG_GND
Ground reference pins for the four output amplifiers.
22
23
24
Exposed
Paddle
VOUTD
VOUTC
AVDD
AVSS
Analog Output Voltage of DAC D. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Analog Output Voltage of DAC C. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Positive Analog Supply Pin. Voltage ranges from 4.5 V to 16.5 V.
Negative Analog Supply connection. Voltage ranges from –4.5 V to –16.5 V. This paddle can be connected to
0 V if output ranges are unipolar.
1 Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high.
Rev. PrC | Page 12 of 32

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