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PDF AD7625 Data sheet ( Hoja de datos )
| Número de pieza | AD7625 | |
| Descripción | 6MSPS PulSAR Differential ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Preliminary Technical Data
FEATURES
Throughput: 6 MSPS
SAR architecture
16-bit resolution with no missing codes
SNR: 92 dB Typ, 90dB Min @ 1MHz
INL: ±1 LSB Typ, ±2 LSB Max
DNL: ±0.3 LSB Typ, ±1 LSB Max
Differential input range: ± 4.096V
No latency/no pipeline delay (SAR architecture)
Serial LVDS interface:
Self-clocked mode
Echoed-clock mode
Reference:
Internal 4.096 V
External (1.2V) buffered to 4.096 V
External 4.096 V
Power dissipation 150 mW
32-Lead LFCSP package (5 mm x 5 mm)
APPLICATIONS
High dynamic range telecommunications
Receivers
Digital imaging systems
High-speed data acquisition
Spectrum analysis
Test equipment
Table 1. Fast PulSAR ADC Selection
Input Type
Res
(Bit
s)
≥1 MSPS
to
< 2MSPS
≥ 2 MSPS
to
≤ 3 MSPS
Differential 16 AD7653
(ground
AD7667
sense)
AD7980
AD7983
AD7985
True Bipolar 16 AD7671
Differential 16
(anti-phase)
AD7677
AD7623
AD7621
AD7622
Differential 18
(anti-phase)
AD7643
AD7982
AD7984
AD7641
AD7986
6 MSPS
AD7625
10
MSPS
AD7626
16-Bit, 6MSPS PulSAR
Differential ADC
AD7625
FUNCTIONAL BLOCK DIAGRAM
REFIN REF VCM
1.2V
BANDGAP
IN+
CAP DAC
IN-
2
CLOCK
AD7626
SAR
LOGIC
SERIAL
LVDS
VIO
CNV
D
DCO
CLK
Figure 1.
GENERAL DESCRIPTION
The AD7625 is a 16-bit, 6MSPS, charge redistribution successive
approximation register (SAR) architecture, analog-to-digital
converter (ADC). SAR architecture allows unmatched
performance both in noise – 92dB SNR - and in linearity –
1LSB. The AD7625 contains a high speed 16-bit sampling ADC,
an internal conversion clock, and an internal buffered reference.
On the CNV edge, it samples the voltage difference between
IN+ and IN− pins. The voltages on these pins swing in opposite
phase between 0 V and REF. The 4.096V reference voltage, REF,
can be generated internally or applied externally.
All converted results are available on a single LVDS self-clocked
or echoed-clock serial interface reducing external hardware
connections.
The AD7625 is housed in a 32-lead LFCSP (5mm by 5mm) with
operation specified from −40°C to +85°C.
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
1 page  
Preliminarywww.DataSheet4U.com Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Analog Inputs/Outputs
CAP1, REFIN
IN+, IN-, REF, REF/2,
CAP2
Digital Inputs/Outputs
Supply Voltage
VDD1
VDD2, VIO
With
Rating
Respect to
GND
GND
GND
-0.3V to 2.7V
-0.3V to 6V
-0.3V to 2.7V
GND
GND
-0.3V to 6V
-0.3V to 2.7V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
AD7625
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type
θJA θJC Unit
ESD CAUTION
Rev. PrB | Page 5 of 11
5 Page 
Preliminarywww.DataSheet4U.com Technical Data
AD7625
OUTLINE DIMENSIONS
PIN 1
INDICATOR
5.00
BSC SQ
TOP
VIEW
4.75
BSC SQ
12° MAX
0.80 MAX
0.65 TYP
0.60 MAX
0.50
BSC
0.50
0.40
0.30
0.60 MAX
25
24
32 1
EXPOSED
PAD
(BOTTOM VIEW)
PIN 1
INDICATOR
3.45
3.30 SQ
3.15
17
16
98
0.25 MIN
3.50 REF
0.05 MAX
1.00 0.02 NOM
0.85 0.30
0.80
SEATING
0.23
0.20 REF
PLANE
0.18
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 5.32-Lead Lead Frame Chip Scale package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-3)
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR07652-0-6/08(PrB)
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet AD7625.PDF ] | |
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