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ADN2526 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADN2526
Beschreibung 11.3 Gbps Active Back-Termination Differential Laser Diode Driver
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
ADN2526 Datasheet, Funktion
www.DataSheet4U.com
11.3 Gbps Active Back-Termination,
Differential Laser Diode Driver
ADN2526
FEATURES
3.3 V operation
Up to 11.3 Gbps operation
Typical 24 ps rise/fall times
Full back-termination of output transmission lines
Drives TOSAs with resistances ranging from 5 Ω to 50 Ω
Bias current range: 10 mA to 100 mA
Differential modulation current range: 10 mA to 80 mA
Voltage input control for bias and modulation currents
Data inputs sensitivity: 150 mV p-p diff
Automatic laser shutdown (ALS)
Cross point adjustment (CPA)
XFP-compliant bias current monitor
SFP+ MSA compliant
Optical evaluation board available
Compact 3 mm × 3 mm LFCSP
APPLICATIONS
SONET OC-192 and SDH STM-64 optical transceivers
10 Gb Fibre Channel transceivers
10 Gb Ethernet optical transceivers
SFP+/XFP/X2/XENPAK/XPAK/MSA 300 optical modules
GENERAL DESCRIPTION
The ADN2526 laser diode driver is designed for direct modula-
tion of packaged laser diodes that have a differential resistance
ranging from 5 Ω to 50 Ω. The active back-termination in the
ADN2526 absorbs signal reflections from the TOSA end of the
output transmission lines, enabling excellent optical eye quality to
be achieved even when the TOSA end of the output transmission
lines is significantly misterminated. ADN2526 is an SFP+ MSA-
compliant device, and its small package and enhanced ESD
protection provide the optimum solution for compact modules
where laser diodes are packaged in low pin-count optical
subassemblies.
The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with control
voltages, the user has the flexibility to implement various
average optical power and extinction ratio control schemes,
including closed-loop or look-up table control. The automatic
laser shutdown (ALS) feature allows the user to turn on/off the
bias and modulation currents by driving the ALS pin with a
LVTTL logic source.
The product is available in a space-saving 3 mm × 3 mm LFCSP
specified from −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
VCC
CPA
ALS
VCC
VCC ADN2526
DATAP
DATAN
50
50
GND
CROSS
POINT
ADJUST
50IMOD
VCC
800
800
IMODP
IMODN
IBMON
IBIAS
200
200
2002
MSET
VEE
BSET
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.






ADN2526 Datasheet, Funktion
ADN2526www.DataSheet4U.com
ABSOLUTE MAXIMUM RATINGS
VEE connected to supply ground.
Table 3.
Parameter
Supply Voltage, VCC to VEE
IMODP, IMODN to VEE
DATAP, DATAN to VEE
All Other Pins
HBM ESD on IMODP, IMODN
HBM ESD on All Other Pins
Junction Temperature
Storage Temperature Range
Soldering Temperature
(Less Than 10 sec)
Rating
−0.3 V to +4.2 V
1.1 V to 4.75 V
VCC − 1.8 V to VCC − 0.4 V
−0.3 V to VCC + 0.3 V
200 V
1 kV
150°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 6 of 16

6 Page









ADN2526 pdf, datenblatt
ADN2526www.DataSheet4U.com
VCC
VCC
MSET
800
200
Figure 26. Equivalent Circuit of the MSET Pin
VCC IMODN
25
IMODP VCC
25
3.33.3
Figure 27. Equivalent IMODP and IMODN Pins, As Seen From Laser Side
The recommended configuration of the MSET, IMODP,
and IMODN pins is shown in Figure 28. See Table 7 for the
recommended components.
VMSET
IBIAS
VCC
ADN2526
IMODP
LL
Z0 = 25C Z0 = 25
MSET IMODN
VEE
Z0 = 25C Z0 = 25
LL
TOSA
Using the resistance of the TOSA, the user can calculate the
voltage range that should be applied to the MSET pin to generate
the required modulation current range (see the example in the
Applications Information section).
The circuit used to drive the MSET voltage must be able to
drive the 1 kΩ resistance of the MSET pin. To be able to drive
80 mA modulation currents through the differential load, the
output stage of the ADN2526 (the IMODP and IMODN pins)
must be ac-coupled to the load. The voltages at these pins have
a dc component equal to VCC and an ac component with
single-ended, peak-to-peak amplitude of IMOD × 25 Ω. This is
the case even if the load impedance is less than 50 Ω differential,
because the transmission line characteristic impedance sets the
peak-to-peak amplitude. For proper operation of the output stage,
the voltages at the IMODP and IMODN pins must be between
the compliance voltage specifications for these pins over supply,
temperature, and modulation current range, as shown in Figure 30.
See the Applications Information section for examples of
headroom calculations.
IMODP, IMODN
VCC + 1.1V
VCC
VCC – 1.1V
NORMAL OPERATION REGION
VCC VCC
Figure 28. Recommended Configuration for the MSET, IMODP, and IMODN Pins
The ratio between the voltage applied to the MSET pin and the
differential modulation current available at the IMODP and
IMODN pins is a function of the load resistance value, as shown
in Figure 29.
220
210
200
190
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
0
MAXIMUM
TYPICAL
MINIMUM
10 20 30 40 50
DIFFERENTIAL LOAD RESISTANCE ()
60
Figure 29. MSET Voltage-to-Modulation Current Ratio vs.
Differential Load Resistance
Figure 30. Allowable Range for the Voltage at IMODP and IMODN
LOAD MISTERMINATION
Due to its excellent S22 performance, the ADN2526 can drive
differential loads that range from 5 Ω to 50 Ω. In practice, many
TOSAs have differential resistance less than 50 Ω. In this case, with
50 Ω differential transmission lines connecting the ADN2526 to
the load, the load end of the transmission lines are misterminated.
This mistermination leads to signal reflections back to the driver.
The excellent back-termination in the ADN2526 absorbs these
reflections, preventing their reflection back to the load. This
enables excellent optical eye quality to be achieved, even when
the load end of the transmission lines is significantly mistermi-
nated. The connection between the load and the ADN2526 must
be made with 50 Ω differential (25 Ω single-ended) transmission
lines so that the driver end of the transmission lines is properly
terminated.
Rev. A | Page 12 of 16

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