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PDF ADV3203 Data sheet ( Hoja de datos )
| Número de pieza | ADV3203 | |
| Descripción | (ADV3202 / ADV3203) 32 X 16 Buffered Analog Crosspoint Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Large, 32 × 16, nonblocking switch array
G = +1 (ADV3202) or G = +2 (ADV3203) operation
32 × 32 pin-compatible version available (ADV3200/ADV3201)
Single +5 V, dual ±2.5 V, or dual ±3.3 V supply (G = +2)
Serial programming of switch array
2:1 OSD insertion mux per output
Input sync-tip clamp
High impedance output disable allows connection of
multiple devices with minimal output bus load
Excellent video performance
60 MHz 0.1 dB gain flatness
0.1% differential gain error (RL = 150 Ω)
0.1° differential phase error (RL = 150 Ω)
Excellent ac performance
Bandwidth: >300 MHz
Slew rate: >400 V/μs
Low power: 1 W
Low all hostile crosstalk: −48 dB @ 5 MHz
Reset pin allows disabling of all outputs
Connected through a capacitor to ground, provides
power-on reset capability
176-lead exposed pad LQFP package (24 mm × 24 mm)
APPLICATIONS
CCTV surveillance
Routing of high speed signals, including
Composite video (NTSC, PAL, S, SECAM)
RGB and component video routing
Compressed video (MPEG, wavelet)
Video conferencing
GENERAL DESCRIPTION
The ADV3202/ADV3203 are 32 × 16 analog crosspoint switch
matrices. They feature a selectable sync-tip clamp input for
ac-coupled applications and a 2:1 on-screen display (OSD)
insertion mux. With −48 dB of crosstalk and −80 dB isolation
at 5 MHz, the ADV3202/ADV3203 are useful in many high
density routing applications. The 0.1 dB flatness out to 60 MHz
makes the ADV3202/ADV3203 ideal for both composite and
component video switching.
The 16 independent output buffers of the ADV3202/ADV3203
can be placed into a high impedance state for paralleling cross-
point outputs so that off-channels present minimal loading to
300 MHz, 32 × 16 Buffered
Analog Crosspoint Switch
ADV3202/ADV3203
FUNCTIONAL BLOCK DIAGRAM
VPOS VNEG DVCC DGND
CLK
DATA IN
193-BIT SHIFT REGISTER
UPDATE
CS
RESET
ENABLE/
BYPASS
97 96
PARALLEL LATCH
96
16 × 5:32
DECODERS
ADV3202
(ADV3203)
16 ENABLE/
DISABLE
SYNC-TIP
CLAMP
512
OUTPUT
BUFFER
G = +1
(G = +2)
DATA
OUT
32
INPUTS
...
...
SWITCH OSD
... ...MATRIX MUX
16
OUTPUTS
16
REFERENCE
16
VCLAMP
OSD
OSD VREF
INPUTS SWITCHES
Figure 1.
an output bus if building a larger array. The ADV3202 has a
gain of +1 while the ADV3203 has a gain of +2 for ease of use in
back-terminated load applications. A single +5 V supply, dual
±2.5 V supplies, or dual ±3.3 V supplies (G = +2) can be used
while consuming only 195 mA of idle current with all outputs
enabled. The channel switching is performed via a double
buffered, serial digital control that can accommodate daisy
chaining of several devices.
The ADV3202/ADV3203 are packaged in a 176-lead exposed
pad LQFP package (24 mm× 24 mm) and are available over the
extended industrial temperature range of −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
1 page  
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TIMING CHARACTERISTICS (SERIAL MODE)
Specifications subject to change without notice.
Table 3.
Parameter
Serial Data Setup Time
CLK Pulse Width
Serial Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulse Width
CLK to DATA OUT Valid
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode
RESET Time
Symbol
t1
t2
t3
t4
t5
t6
t7
ADV3202/ADV3203
Limit
Min Typ Max Unit
40 ns
50 ns
50 ns
150 ns
50 160 ns
40 ns
130 ns
50 ns
38.6 μs
160 ns
1
CS
0
1
CLK
0
1
DATA IN
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
DATA OUT
t2
t1 t3
CLAMP
ON/OFF
t7
t4 LOAD DATA INTO
SERIAL REGISTER
ON RISING EDGE
OUT15 (D5)
OUT00 (D0)
t5
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t6
Figure 2. Timing Diagram, Serial Mode
Table 4. Logic Levels, DVCC = 3.3 V
VIH
RESET, CS,
CLK, DATA IN,
UPDATE, OSDS
VIL
RESET, CS,
CLK, DATA IN,
UPDATE, OSDS
VOH
DATA OUT
2.5 V min
0.8 V max
2.7 V min
VOL
DATA OUT
0.5 V max
IIH
RESET, CS,
CLK, DATA IN,
UPDATE, OSDS
0.5 μA typ
IIL
RESET, CS,
CLK, DATA IN,
UPDATE, OSDS
−0.5 μA typ
IOH
DATA OUT
3 mA typ
IOL
DATA OUT
−3 mA typ
Rev. 0 | Page 5 of 20
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ADV3202/ADV3203
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±2.5 V (ADV3202), VS = ±3.3 V (ADV3203) at TA = 25°C, RL = 150 Ω.
2
INxx
0
–2
OSDxx
–4
–6
–8
–10
–12
1
10 100
FREQUENCY (MHz)
1k
Figure 5. ADV3202 Small Signal Frequency Response, 200 mV p-p
1.2
0.8
0.4
0
–0.4
–0.8
INxx
OSDxx
–1.2
0 2 4 6 8 10 12 14 16 18 20
TIME (ns)
Figure 8. ADV3202 Large Signal Pulse Response, 2 V p-p
2
0
–2
–4
–6
OSDxx
–8
INxx
–10
–12
1
10 100
FREQUENCY (MHz)
1k
Figure 6. ADV3202 Large Signal Frequency Response, 2 V p-p
0.12
0.08
0.04
0
–0.04
OSDxx
–0.08
INxx
–0.12
0 2 4 6 8 10 12 14 16 18 20
TIME (ns)
Figure 7. ADV3202 Small Signal Pulse Response, 200 mV p-p
600
400
RISING EDGE
200
0
–200
–400
FALLING EDGE
–600
0 2 4 6 8 10 12 14 16 18 20
TIME (ns)
Figure 9. ADV3202 Slew Rate
0.05
0.04
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.7
–0.5
–0.3 –0.1
0.1
0.3
INPUT DC OFFSET (V)
0.5
0.7
Figure 10. ADV3202 Differential Gain, Carrier Frequency = 3.58 MHz,
Subcarrier Amplitude = 300 mV p-p
Rev. 0 | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADV3203.PDF ] | |
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