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PDF AD9552 Data sheet ( Hoja de datos )
| Número de pieza | AD9552 | |
| Descripción | Oscillator Frequency Up Converter | |
| Fabricantes | Analog Devices | |
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Hay una vista previa y un enlace de descarga de AD9552 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Data Sheet
Oscillator Frequency Upconverter
AD9552
FEATURES
Converts a low frequency input reference signal to a high
frequency output signal
Input frequencies from 6.6 MHz to 112.5 MHz
Output frequencies up to 900 MHz
Preset pin programmable frequency translation ratios
Arbitrary frequency translation ratios via SPI port
On-chip VCO
Accepts a crystal resonator and/or an external oscillator
as a reference frequency source
Secondary output (either integer-related to the primary
output or a copy of the reference input)
RMS jitter: <0.5 ps
SPI-compatible, 3-wire programming interface
Single supply (3.3 V)
Very low power: <400 mW (under most conditions)
Small package size (5 mm × 5 mm)
APPLICATIONS
Cost effective replacement of high frequency VCXO, OCXO,
and SAW resonators
Extremely flexible frequency translation with low jitter for
SONET/SDH (including FEC), 10 Gb Ethernet, Fibre
Channel, and DRFI/DOCSIS
High-definition video frequency translation
Wireless infrastructure
Test and measurement (including handheld devices)
GENERAL DESCRIPTION
The AD9552 is a fractional-N phase locked loop (PLL) based
clock generator designed specifically to replace high frequency
crystal oscillators and resonators. The device employs a sigma-
delta (Σ-Δ) modulator (SDM) to accommodate fractional
frequency synthesis. The user supplies an input reference signal
by connecting a single-ended clock signal directly to the REF
pin or by connecting a crystal resonator across the XTAL pins.
The AD9552 is pin programmable, providing one of 64 standard
output frequencies based on one of eight common input
frequencies. The device also has a 3-wire SPI interface, enabling
the user to program custom input-to-output frequency ratios.
The AD9552 relies on an external capacitor to complete the loop
filter of the PLL. The output is compatible with LVPECL, LVDS,
or single-ended CMOS logic levels, although the AD9552 is
implemented in a strictly CMOS process.
The AD9552 is specified to operate over the extended industrial
temperature range of −40°C to +85°C.
REF
XTAL
BASIC BLOCK DIAGRAM
AD9552
INPUT
FREQUENCY
SOURCE
SELECTOR
PLL
OUTPUT
CIRCUITRY
PIN-DEFINED AND SERIAL PROGRAMMING
OUT2
OUT1
Figure 1.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9552
Data Sheet
Parameter
Input Capacitance
Input Resistance
Duty Cycle
Input Voltage
Input High Voltage, VIH
Input Low Voltage, VIL
Input Threshold Voltage
VCO CHARACTERISTICS
Frequency Range
Upper Bound
Lower Bound
VCO Gain
VCO Tracking Range
VCO Calibration Time
Min Typ Max Unit
3 pF
130 kΩ
40 60 %
1.62
1.0
V
0.52 V
V
Test Conditions/Comments
When ac coupling to the input receiver, the user must dc bias the input
to 1 V
±300
4050
3350
45
140
MHz
MHz
MHz/V
ppm
μs
fPFD7 = 77.76 MHz; time between completion of the VCO calibration
command (the rising edge of CS (Pin 12)) to the rising edge of LOCKED
(Pin 20).
1 The A[2:0], Y[5:0], and OUTSEL pins have 100 kΩ internal pull-up resistors.
2 The RESET pin has a 100 kΩ internal pull-up resistor, so the default state of the device is reset.
3 N is the integer part of the feedback divider.
4 Sigma-delta modulator.
5 The minimum allowable feedback divider value with the SDM disabled.
6 The minimum allowable feedback divider value with the SDM enabled.
7 The frequency at the input to the phase-frequency detector.
CRYSTAL INPUT CHARACTERISTICS
Table 2.
Parameter
CRYSTAL FREQUENCY
Range
Tolerance
CRYSTAL MOTIONAL RESISTANCE
CRYSTAL LOAD CAPACITANCE
Min
10
Typ
26
15
Max
52
20
100
Unit
MHz
ppm
Ω
pF
Test Conditions/Comments
Using a crystal with a specified load capacitance other than
15 pF (8 pF to 24 pF) is possible, but necessitates using the
SPI port to configure the AD9552 crystal input capacitance.
OUTPUT CHARACTERISTICS
Table 3.
Parameter
LVPECL MODE
Differential Output Voltage Swing
Common-Mode Output Voltage
Frequency Range
Duty Cycle
Rise/Fall Time1 (20% to 80%)
Min Typ Max Unit
690
VDD − 1.77
0
40
765
VDD − 1.66
255
889
VDD − 1.20
900
60
305
mV
V
MHz
%
ps
Test Conditions/Comments
Output driver static
Output driver static
Up to 805 MHz output frequency
100 Ω termination between both pins of
the output driver
Rev. E | Page 4 of 32
5 Page 
AD9552
25
20
15
10
5
0
0 50 100 150 200
FREQUENCY (MHz)
Figure 9. Supply Current vs. Output Frequency,
CMOS (15 pF Load)
250
4.0
3.5
5pF
3.0
10pF
2.5
20pF
2.0
1.5
1.0
0.5
0
0 100 200 300 400 500
FREQUENCY (MHz)
Figure 10. Peak-to-Peak Output Voltage vs. Frequency,
CMOS
55
54
5pF
10pF
20pF
53
52
51
50
0 100 200
FREQUENCY (MHz)
Figure 11. Duty Cycle vs. Output Frequency, CMOS
300
Data Sheet
1.6
LVPECL
1.4
1.2
LVDS (STRONG)
1.0
0.8
LVDS (WEAK)
0.6
0.4
0
200 400 600 800
FREQUENCY (MHz)
1000
Figure 12. Peak-to-Peak Output Voltage vs. Frequency,
LVPECL and LVDS (15 pF Load)
60
55
50
100
LVDS (WEAK)
LVDS (STRONG)
LVPECL
200 300 400 500 600 700 800 900
FREQUENCY (MHz)
Figure 13. Duty Cycle vs. Output Frequency,
LVPECL and LVDS (15 pF Load)
1000
500ps/DIV
Figure 14. Typical Output Waveform, LVPECL (805 MHz)
Rev. E | Page 10 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9552.PDF ] | |
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