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GS9090 Schematic ( PDF Datasheet ) - Gennum Corporation

Teilenummer GS9090
Beschreibung GenLINX-R III 270Mb/s Deserializer
Hersteller Gennum Corporation
Logo Gennum Corporation Logo 




Gesamt 30 Seiten
GS9090 Datasheet, Funktion
www.DataSheet4U.com
GS9090 GenLINX® III 270Mb/s
Deserializer for SDI and DVB-ASI
GS9090 Data Sheet
Key Features
• SMPTE 259M-C compliant descrambling and NRZI
to NRZ decoding (with bypass)
• DVB-ASI sync word detection and 8b/10b decoding
• Integrated line-based FIFO for data
alignment/delay, clock phase interchange, DVB-ASI
data packet extraction and clock rate interchange,
and ancillary data packet extraction
• Integrated VCO and reclocker
• Automatic or manual selection between SMPTE
video and DVB-ASI data
• Single serial digital input buffer with wide input
sensitivity
• User selectable additional processing features
including:
• TRS, ANC data checksum, and EDH CRC error
detection and correction
• programmable ANC data detection
• illegal code remapping
• Internal flywheel for noise immune H, V, F
extraction
• Automatic standards detection and indication
• Enhanced Gennum Serial Peripheral Interface
(GSPI)
• JTAG test interface
• Polarity insensitive for DVB-ASI and SMPTE
signals
• +1.8V core power supply with optional +1.8V or
+3.3V I/O power supply
• Small footprint (8mm x 8mm)
• Low power operation (typically 145mW)
• Pb-free and RoHS compliant
Applications
• SMPTE 259M-C Serial Digital Interfaces
• DVB-ASI Serial Digital Interfaces
Description
The GS9090 is a 270Mb/s reclocking deserializer with
an internal FIFO. When used in conjunction with one of
Gennum’s SDI Cable Equalizers, a receive solution for
SD-SDI and DVB-ASI applications can be realized.
In addition to reclocking and deserializing the input data
stream, the GS9090 performs NRZI-to-NRZ decoding,
descrambling as per SMPTE 259M-C, and word
alignment when operating in SMPTE mode. When
operating in DVB-ASI mode, the device will word align
the data to K28.5 sync characters and 8b/10b decode
the received stream.
The integrated reclocker features a very wide Input
Jitter Tolerance, and is fully compatible with both
SMPTE and DVB-ASI input streams.
The GS9090 includes a range of data processing
functions such as error detection and correction,
automatic standards detection, and EDH support. The
device can also detect and extract SMPTE 352M
payload identifier packets and independently identify
the received video standard. This information is read
from internal registers via the host interface port.
TRS errors, EDH CRC errors, and ancillary data
checksum errors can all be detected and corrected. A
single DATA_ERROR pin is provided which is an
inverted logical 'OR'ing of all detectable errors.
Individual error status is stored in internal
‘ERROR_STATUS’ registers.
The GS9090 also incorporates a video line-based FIFO.
This FIFO may be used in four user-selectable modes
to carry out tasks such as data alignment / delay, clock
phase interchange, MPEG packet extraction and clock
rate interchange, and ancillary data packet extraction.
Parallel data outputs are provided in 10-bit multiplexed
format, with the associated parallel clock output signal
operating at 27MHz.
The GS9090 is Pb-free, and the encapsulation
compound does not contain halogenated flame
retardant (RoHS compliant).
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GS9090 Datasheet, Funktion
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1.2 Pin Descriptions
GS9090 Data Sheet
Table 1-1: Pin Descriptions
Pin
Number
1
Name
LF-
2 PLL_GND
3 PLL_VDD
4 BUFF_VDD
5, 6
7
8
9, 11
10
12
DDI, DDI
BUFF_GND
TERM
NC
VBG
IOPROC_EN
Timing
Type Description
Analog
Analog
Analog
Analog
Input
Input
Power
Input
Power
Input
Power
Analog
Analog
Analog
Analog
Input
Input
Power
Input
Input
Non Input
Synchronous
Loop filter component connection. Connect to pin 56 (LF+) as shown in
the Typical Application Circuit (Part B) on page 67.
Ground connection for phase-locked loop. Connect to GND.
Power supply connection for phase-locked loop. Connect to +1.8V DC.
Power supply connection for digital input buffers.
When operating with 1.8V input as required by the current silicon this
pin should be left unconnected.
When operating with 3.3V input (available in future silicon) this pin
should be connected to +3.3V as shown in the Typical Application
Circuit (Part B) on page 67.
Serial digital differential input pair.
Ground connection for serial digital input buffer. Connect to GND.
Termination for serial digital input. AC couple to BUFF_GND
No connect.
Bandgap filter capacitor. Connect to GND as shown in the Typical
Application Circuit (Part B) on page 67.
CONTROL SIGNAL INPUT
Signal Levels are LVCMOS / LVTTL compatible.
Used to enable or disable the I/O processing features.
When set HIGH, the following I/O processing features of the device are
enabled:
• Illegal Code Remapping
• EDH CRC Error Correction
• Ancillary Data Checksum Error Correction
• TRS Error Correction
• EDH Flag Detection
To enable a subset of these features, keep the IOPROC_EN pin HIGH
and disable the individual feature(s) in the IOPROC_DISABLE register
accessible via the host interface.
When set LOW, the device will enter low-latency mode.
NOTE: When the internal FIFO is configured for Video mode or
Ancillary Data Extraction mode, the IOPROC_EN pin must be set
HIGH (see Internal FIFO Operation on page 46).
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2. Electrical Characteristics
GS9090 Data Sheet
2.1 Absolute Maximum Ratings
Table 2-1: Absolute Maximum Ratings
Parameter
Supply Voltage Core
Supply Voltage I/O
Input Voltage Range (any input)
Ambient Operating Temperature
Storage Temperature
ESD protection on all pins (see note 2)
NOTES:
1. See reflow solder profile
2. HBM, per JESDA - 114B
Value/Units
-0.3V to +2.1V
-0.3V to +3.47V
-2.0V to + 5.25V
-20°C < TA < 85°C
-40°C < TSTG < 125°C
1kV
2.2 DC Electrical Characteristics
Table 2-2: DC Electrical Characteristics
VDD = 1.8V, TA = 0°C to 70°C, unless otherwise specified.
Parameter
Symbol
Condition
Min Typ Max Units Notes
System
Operating Temperature Range
Core power supply voltage
Digital I/O Buffer Power Supply
Voltage
PLL Power Supply Voltage
VCO Power Supply Voltage
Typical System Power
Max. System Power
TA
0 25 70 °C
CORE_VDD –
1.71 1.8 1.89
V
IO_VDD
1.8V Operation
1.71 1.8 1.89
V
IO_VDD
3.3V Operation
3.13 3.3 3.47
V
PLL_VDD
1.71 1.8 1.89
V
VCO_VDD
1.71 1.8 1.89
V
PD
CORE_VDD = 1.8V
145
mW
IO_VDD = 1.8V
T = 25oC
PD
CORE_VDD = 1.89V
– 200 mW
IO_VDD = 3.47V
T = 70oC
1
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