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PDF ADUM3211 Data sheet ( Hoja de datos )
| Número de pieza | ADUM3211 | |
| Descripción | Enhanced System-Level ESD Reliability | |
| Fabricantes | Analog Devices | |
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Dual-Channel Digital Isolators,
Enhanced System-Level ESD Reliability
ADuM3210/ADuM3211
FEATURES
Enhanced system-level ESD performance per IEC 61000-4-x
High temperature operation: 125°C
Default low output
Narrow body, RoHS-compliant, 8-lead SOIC
Low power operation
5 V operation
1.6 mA per channel maximum @ 0 Mbps to 2 Mbps
3.7 mA per channel maximum @ 10 Mbps
3 V operation
1.4 mA per channel maximum @ 0 Mbps to 2 Mbps
2.4 mA per channel maximum @ 10 Mbps
3 V/5 V level translation
High data rate: dc to 10 Mbps (NRZ)
Precise timing characteristics
3 ns maximum pulse width distortion at 5 V operation
3 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
VIORM = 560 V peak
APPLICATIONS
Size-critical multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceiver isolation
Digital field bus isolation
Gate drive interface
GENERAL DESCRIPTION
The ADuM321x1 are dual-channel, digital isolators based on
Analog Devices, Inc., iCoupler® technology. Combining high
speed CMOS and monolithic transformer technology, this
isolation component provides outstanding performance charac-
teristics superior to alternatives such as optocoupler devices.
By avoiding the use of LEDs and photodiodes, iCoupler
devices remove the design difficulties commonly associated
with optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance charac-
teristics. The need for external drivers and other discrete
components is eliminated with these iCoupler products.
Furthermore, iCoupler devices consume one-tenth to one-
sixth the power of optocouplers at comparable signal data rates.
The ADuM321x isolators provide two independent isolation
channels. They operate with the supply voltage on either side
ranging from 2.7 V to 5.5 V, providing compatibility with lower
voltage systems as well as enabling voltage translation functionality
across the isolation barrier. The ADuM321x isolators have a
default output low characteristic in comparison to the ADuM3200/
ADuM3201 models that have a default output high characteristic.
The ADuM321x are also available in 125°C temperature grade.
In comparison to the ADuM120x isolator, the ADuM321x
isolators contain various circuit and layout changes providing
increased capability relative to system-level IEC 61000-4-x
testing (ESD, burst, and surge). The precise capability in these
tests for either the ADuM120x or ADuM321x products is strongly
determined by the design and layout of the user’s board or
module. For more information, see the AN-793 Application
Note, ESD/Latch-Up Considerations with iCoupler Isolation
Products.
FUNCTIONAL BLOCK DIAGRAMS
VDD1 1
ADuM3210
8 VDD2
VIA 2
ENCODE
DECODE
7 VOA
VIB 3
ENCODE
DECODE
6 VOB
GND1 4
5 GND2
Figure 1. ADuM3210 Functional Block Diagram
VDD1 1
ADuM3211
8 VDD2
VOA 2
ENCODE
DECODE
7 VIA
VIB 3
ENCODE
DECODE
6 VOB
GND1 4
5 GND2
Figure 2. ADuM3211 Functional Block Diagram
1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239. Other patents pending.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
1 page  
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ADuM3210/ADuM3211
ADuM3210 ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION
All voltages are relative to their respective ground. 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications
apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V.
Table 2.
Parameter
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent
Output Supply Current, per Channel, Quiescent
Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps
VDD1 Supply Current
VDD2 Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Symbol
IDDI (Q)
IDDO (Q)
IDD1 (Q)
IDD2 (Q)
IDD1 (10)
IDD2 (10)
IIA, IIB
VIH
VIL
Min
−10
0.7 × (VDD1
or VDD2)
Logic High Output Voltages
Logic Low Output Voltages
VOAH
VOBH
VOAL
VOBL
(VDD1 or
VDD2) − 0.1
(VDD1 or
VDD2) − 0.5
SWITCHING SPECIFICATIONS
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
Channel-to-Channel Matching,
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output7
Common-Mode Transient Immunity
at Logic Low Output7
Refresh Rate
Input Dynamic Supply Current, per Channel8
Output Dynamic Supply Current, per Channel8
PW
tPHL, tPLH
PWD
10
20
tPSK
tPSKCD
tPSKOD
tR/tF
|CMH|
|CML|
fr
IDDI (D)
IDDO (D)
25
25
Typ Max
0.3 0.5
0.3 0.5
0.8 1.3
0.7 1.0
2.0 3.2
1.1 1.7
+0.01 +10
0.3 × (VDD1
or VDD2)
3.0
2.8
0.0 0.1
0.04 0.1
0.2 0.4
100
60
3
5
22
3
22
3.0
35
35
1.1
0.10
0.03
Unit Test Conditions
mA
mA
mA DC to 1 MHz logic signal freq.
mA DC to 1 MHz logic signal freq.
mA 5 MHz logic signal freq.
mA 5 MHz logic signal freq.
μA 0 ≤ VIA, VIB, ≤ VDD1 or VDD2
V
V
V IOx = −20 μA, VIx = VIxH
V IOx = −4 mA, VIx = VIxH
V IOx = 20 μA, VIx = VIxL
V IOx = 400 μA, VIx = VIxL
V IOx = 4 mA, VIx = VIxL
ns
Mbps
ns
ns
ps/°C
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
ns CL = 15 pF, CMOS signal levels
ns
kV/μs
kV/μs
Mbps
mA/Mbps
mA/Mbps
CL = 15 pF, CMOS signal levels
VIx = VDD1, VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total VDD1 and VDD2 supply currents as a function of data rate.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
Rev. B | Page 5 of 28
5 Page 
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ADuM3210/ADuM3211
ADuM3210 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation:
2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operating range,
unless otherwise noted. All typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5.0 V; or VDD1 = 5.0 V, VDD2 = 3.0 V.
Table 5.
Parameter
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current, per Channel, Quiescent
5 V/3 V Operation
3 V/5 V Operation
Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
10 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|3
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Channel-to-Channel Matching
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3 V/5 V Operation
Symbol
IDDI (Q)
Min
IDDO (Q)
Typ Max
0.4 0.8
0.3 0.5
0.3 0.5
0.5 0.6
Unit
mA
mA
mA
mA
IDD1 (Q)
IDD2 (Q)
1.3 1.7
0.8 1.3
0.7 1.0
1.0 1.6
mA
mA
mA
mA
IDD1 (10)
IDD2 (10)
3.5 4.6
2.0 3.2
1.1 1.7
1.7 2.8
mA
mA
mA
mA
IIA, IIB
VIH
VIL
VOAH, VOBH
VOAL, VOBL
−10
0.7 × (VDD1
or VDD2)
0.8
0.4
(VDD1 or
VDD2) − 0.1
(VDD1 or
VDD2) − 0.5
+0.01
+10
0.3 × (VDD1
or VDD2)
(VDD1 or
VDD2)
VDD1,
VDD2 − 0.2
0.0
0.04
0.2
0.1
0.1
0.4
μA
V
V
V
V
V
V
V
V
V
PW
tPHL, tPLH
PWD
tPSK
tPSKCD
tPSKOD
tR/tF
10
15
100
55
3
5
22
3
22
3.0
2.5
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
ns
ns
Test Conditions
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
5 MHz logic signal freq.
5 MHz logic signal freq.
5 MHz logic signal freq.
0 ≤ VIA, VIB ≤ VDD1 or VDD2
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Rev. B | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ADUM3211.PDF ] | |
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