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PDF DS34S132 Data sheet ( Hoja de datos )
| Número de pieza | DS34S132 | |
| Descripción | 32-Port TDM-over-Packet IC | |
| Fabricantes | Maxim Integrated Products | |
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19-4750; Rev 0; 7/09
www.DataSheet4U.com
ABRIDGED DATA SHEET
DS34S132
32-Port TDM-over-Packet IC
General Description
The IETF PWE3 SAToP/CESoPSN/HDLC-compliant
DS34S132 provides the interworking functions that
are required for translating TDM data streams into
and out of TDM-over-Packet (TDMoP) data streams
for L2TPv3/IP, UDP/IP, MPLS (MFA-8), and Metro
Ethernet (MEF-8) networks while meeting the jitter
and wander timing performance that is required by
the public network (ITU G.823, G.824, and G.8261).
Up to 32 TDM ports can be translated into as many
as 256 individually configurable pseudowires (PWs)
for transmission over a 100/1000Mbps Ethernet port.
Each TDM port’s bit rate can vary from 64Kbps to
2.048Mbps to support T1/E1 or slower TDM rates.
PW interworking for TDM-based serial HDLC data is
also supported. A built-in time-slot assignment (TSA)
circuit provides the ability to combine any group of
time slots (TS) from a single TDM port into a single
PW. The high level of integration provides the perfect
solution for high-density applications to minimize
cost, board space, and time to market.
Applications
TDM Circuit Emulation Over PSN
TDM Leased-Line Services Over PSN
TDM Over BPON/GPON/EPON
TDM Over Cable
TDM Over Wireless
Cellular Backhaul
Multiservice Over Unified PSN
HDLC-Encapsulated Data Over PSN
Functional Diagram
Features
32 Independent TDM Ports with Serial Data,
Clock, and Sync (Data = 64Kbps to 2.048Mbps)
One 100/1000Mbps (MII/GMII) Ethernet MAC
256 Total PWs, 32 PW per TDM Port, with Any
Combination of TDMoP and/or HDLC PWs
PSN Protocols: L2TPv3 or UDP Over IP (IPv4 or
IPv6), Metro Ethernet (MEF-8), or MPLS (MFA-8)
0, 1, or 2 VLAN Tags (IEEE 802.1Q)
Synchronous or Asynchronous TDM Port
Timing
One Clock Recovery Engine per TDM Port with
One Assignable as a Global Reference
Supported Clock Recovery Techniques
Adaptive Clock Recovery
Differential Clock Recovery
Absolute and Differential Timestamps
Independent Receive and Transmit Interfaces
Two Clock Inputs for Direct Transmit Timing
For Structured T1/E1, Each TDM Port Includes
DS0 TSA Block for any Time Slot to Any PW
32 HDLC/CES Engines (256 Total)
With or Without CAS Signaling
For Unstructured, each TDM Port Includes
One HDLC/SAT Engine (32 Total)
Any data rate from 64Kbps to 2.048Mbps
32-Bit or 16-Bit CPU Processor Bus
CPU-Based OAM and Signaling
UDP-specific
“Special” Ethernet Type
Inband VCCV
ARP
MEF OAM
NDP/IPv6
Broadcast DA
DDR SDRAM Interface
Low-Power 1.8V Core, 3.3V I/O, 2.5V SDRAM
Ordering Information
PART
PORTS TEMP RANGE PIN-PACKAGE
DS34S132 GN
32 -40C to +85C 676 BGA
DS34S132 GN+ 32 -40C to +85C 676 BGA
+Denotes a lead(Pb)-free/RoHS-compliant package.
Maxim Integrated Products 1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
ABRIDGED DATA SHEET
Maxim Integrated Products Confidential and Proprietary
DS34S132 DATA SHEET
www.DataSheet4U.com
4 HIGH LEVEL DESCRIPTION
To implement a PW (tunnel) across a PSN requires a PW termination point at each end of the PW (tunnel). Each
terminating point provides the PW encapsulation functions that are required to enter the PSN (for one direction of
data) and the PW de-encapsulation functions to restore the data to its original (non-PW) format (for the opposite
direction). The two data directions at each termination point can be can be described as the “transmit PW packet
direction” (TXP) and the “receive PW packet direction” (RXP).
The DS34S132 TDMoP device implements the complete, bi-directional PW termination point encapsulation
functions for TDMoP and HDLC PWs. The DS34S132 is a high density solution that can terminate up to 256 PWs
that are associated with up to 32 T1/E1 data streams and aggregate that traffic for transmission over a single
100/1000 Mb/s Ethernet data stream. The DS34S132 can encap/decap TDMoP and HDLC PWs into the following
PSN protocols: L2TPv3/IPv4, L2TPv3/IPv6, UDP/IPv4, UDP/IPv6, Metro Ethernet (MEF-8) and MPLS (MFA-8).
For TDMoP PWs the DS34S132 supports the SAToP and CESoPSN payload formats. SAToP is used for
Unstructured TDM transport, where an entire T1/E1 including the framing pattern (if it exists) is transferred
transparently as a series of unformatted bytes of data in the PW payload without regard to any bit, byte and/or
frame alignment that may exist in the TDM data stream. The DS34S132 can support Unstructured T1, E1 or
slower TDM data streams (any bit rate less than or equal to 2.048 Mb/s).
CESoPSN is used for Structured TDM transport where the PW packet payload is synchronized to the T1/E1
framing. With CESoPSN the T1/E1 framing pattern is commonly not passed across the PW (removed) because the
structured PW format enables the framing information to be conveyed through the PW mechanisms. The opposite
end generates the T1/E1 framing pattern from the PWs payload structure. This payload format can be used when
the TDM service (e.g. voice) requires the ability to interpret, and/or terminate some functional aspects of the T1/E1
signal (e.g. identify DS0s within the T1/E1). PWs with the Structured payload format can support Nx64 Kb/s,
fractional T1/E1 (T1: N = 1 – 24; E1: N = 1 – 32). In some applications, a T1/E1 can be divided into multiple Nx64
blocks (M x N x 64; M = the number of fractional blocks) and the PSN can be used as a “distributed cross-connect”
to implement a point to multi-point topology forwarding some Nx64 blocks to one end point and other Nx64 blocks
to other end points (T1: M = 1 – 24; E1: M = 1 – 32; e.g. for E1: 32 x 1 x 64).
The CESoPSN Structured format can also convey CAS Signaling across a PW through the use of a sub-channel
within the CESoPSN PW packets. The DS34S132 enables the CAS Signaling to be transparently passed,
monitored by an external CPU, and/or terminated by an external CPU, all on a per Timeslot and per direction basis.
The DS34S132 allows each TDM Port to independently support asynchronous or synchronous TDM data streams.
Each TDM Port has a Clock Recovery Engine to regenerate the timing from a TDMoP PW packet data stream. For
applications that do not require clock recovery the DS34S132 also provides several external clocking options.
The Clock Recovery Engines support Differential Clock Recovery (DCR) and Adaptive Clock Recovery (ACR).
DCR can be used when a common clock is available at both ends of the PW (e.g. BITS clock for the public network
or GPS for the mobile cellular network) and requires that the PW use RTP Timestamps to convey the TDM timing
information. Adaptive Clock Recovery does not use Timestamps but instead regenerates the timing based on the
TDMoP PW packet transmission rate. The DS34S132 high performance clock recovery circuits enable the use of
PWs in the public network by achieving the stringent jitter and wander performance requirements of ITU-T
G.823/824/8261, even for networks that impose large packet delay variation (PDV) and packet loss. For far end
clock recovery, the DS34S132 can generate two Timestamp formats - Absolute and Differential Timestamps.
PWs can be used to transport HDLC packet data. The DS34S132 can forward HDLC encapsulated data
transparently using a TDMoP PW (as described above; idle HDLC Flags are forwarded with the data) or by first
extracting the data from the HDLC coding and then only forwarding the non-idle data in an HDLC PW. The HDLC
PW is useful for HDLC data streams where a significant portion of the data stream is filled with HDLC Idle Flags.
For example, if a 64 Kb/s TDM Timeslot is used to carry 4 Kb/s of HDLC data then it may be more bandwidth
efficient to extract the payload data from the HDLC encoding and forward the data over an HDLC PW. The
DS34S132 incorporates 256 HDLC Engines so that any PW can be assigned as a TDMoP PW or an HDLC PW.
PW Termination points often must also terminate OAM and Signaling packet data streams. To support this need
the DS34S132 enables an external CPU to terminate several OAM and Signaling types including: PW In-band
VCCV OAM, PW UDP-specific (Out-band VCCV) OAM, MEF OAM, Ethernet Broadcast frames, ARP, IPv6 NDP
and includes a user specified CPU-destination Ethernet Type. The DS34S132 can also be programmed to forward
packets to the CPU that match specialized conditions for debug or other purposes (e.g. wrong IP DA).
19-4750; Rev 0; 7/09
11 of 194
5 Page 
ABRIDGED DATA SHEET
Maxim Integrated Products Confidential and Proprietary
DS34S132 DATA SHEET
wwwE.DtahtaeSrhneeet4tUP.coomrt Features
Ethernet MAC Interface
100/1000 Mb/s Operation using MII/GMII Interface
2 programmable receive Ethernet Destination Addresses
Mixed Ethernet II (DIX) and IEEE 802.2 LLC/SNAP formats
Mixed data streams with 0, 1, or 2 VLAN Tags
Programmable VLAN TPID
Ethernet Frame Length 64 bytes to 2000 bytes
PW/Bundle Features
RXP PW/Bundle Header
Up to 256 programmed PW/Bundles (32 per TDM Port)
PW Header Types
L2TPv3 / IPv6
UDP / IPv4
MEF (MEF-8)
L2TPv3 / IPv4
UDP / IPv6
MPLS (MFA-8)
Mixed MPLS data streams with 0, 1 or 2 MPLS Outer Labels
Mixed L2TPv3 data streams with 0, 1, or 2 L2TPv3 Cookies
Flexible UDP settings
16-bit (standard) or 32-bit (extended) UDP PW-ID bit width
16-bit UDP PW-ID selectable to be verified against UDP Source or Destination Port
Optional 16-bit PW-ID Mask
Ignore UDP Payload Protocol or verify against 2 programmable UDP Payload Protocol Values
Optional PW Control Word
Optional “In-band VCCV” Monitoring
Programmable 16-bit In-band VCCV value with programmable 16-bit In-band VCCV mask
Optional RTP Header
One PW/Bundle per TDM Port can be assigned to provide RTP Timestamp for Clock Recovery
Sequence Number
Selectable between Control Word or RTP Sequence Number
Used to initiate conditioning data when packets are missing
Optional re-ordering of mis-ordered packets up to the Size of the Jitter Buffer depth
Up to 32 UDP-Specific (Out-band VCCV) OAM PW-IDs
Debug settings to forward PW/Bundles with special conditions to CPU for analysis (e.g. wrong IP DA)
TXP PW/Bundle Header
Store up to 256 CPU generated PW/Bundle Headers (one per PW/Bundle)
Maximum 122 byte header with any CPU-specified content (Layer 2/3/4 content)
Auto generate and insert Length and FCS functions for IP and UDP Headers
Optional RTP Timestamp Insertion
Any number of TXP PW/Bundles can be assigned to include Timestamp in RTP Header
Optional RTP and Control Word Sequence Number Insertion
3 HDLC Sequence Number generation modes
Sequence Numbers with “fixed at zero” value
Sequence Numbers with incremented counting using “skip zero at Rollover”
Sequence Numbers with incremented counting using “include zero at Rollover”
PW/Bundle Payload Types
TDMoP PW/Bundles (non-HDLC) - Constant Bit Rate Services (e.g. PCM voice)
Unstructured PW Payload (without framing; SAToP): E1, T1 and slower TDM bit rate (≤ 2.048 Mb/s)
Structured PW Payload (with framing; CESoPSN)
E1, T1-SF and T1-ESF formats
19-4750; Rev 0; 7/09
17 of 194
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