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PDF CY8C20180 Data sheet ( Hoja de datos )

Número de pieza CY8C20180
Descripción Configurable IOs
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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CY8C20180
CapSense Express™ -8 Configurable IOs
Features
8 configurable IOs supporting
CapSense buttons
LED Drive
Interrupt outputs
WAKE on interrupt input
User defined input or output
2.4V to 5.25V operating voltage
Industrial temperature range: –40°C to +85°C
I2C slave interface for configuration
Selectable to 50 kHz,100 kHz and 400 kHz
Reduce BOM cost
Internal oscillator - no external oscillators or crystal
Free development tool - no external tuning components
Low operating current
Active current: continuous sensor scan:1.5 mA
Sleep current: no scan, continuous sleep: 2.6 uA
Available in 16-pin COL and 16-pin SOIC packages
Overview
The CapSense ExpressTM controller allows the control of 8 IOs
configurable as capacitive sensing buttons or as GPIOs for
driving LEDs or interrupt signals based on various button
conditions. The GPIOs are also configurable for waking up the
device from sleep based on an interrupt input.
The user has the ability to configure buttons, outputs, and
parameters through specific commands sent to the I2C port. The
IOs have the flexibility in mapping to capacitive buttons and as
standard GPIO functions such as interrupt output or input, LED
drive and digital mapping of input to output using simple logical
operations. This enables easy PCB trace routing and reduces
the PCB size and stack up. CapSense Express products are
designed for easy integration into complex products.
Architecture
The logic block diagram illustrates the internal architecture of
CY8C20180.
The user can configure registers with parameters needed to
adjust the operation and sensitivity of the CapSense system.
CY8C20180 supports a standard I2C serial communications
interface that allows the host to configure the device and to read
sensor information in real time through easy register access.
The CapSense Express Core
The CapSense Express Core has a powerful configuration and
control block. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers. System
resources provide additional capability, such as a configurable
I2C slave communication interface and various system resets.
The Analog System is composed of the CapSense PSoC block
which supports capacitive sensing of up to eight inputs.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-17346 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 11, 2008
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CY8C20180
The CapSense Analog System
The CapSense analog system contains the capacitive sensing
hardware. which supports CapSense Successive Approximation
(CSA) algorithm.This hardware performs capacitive sensing and
scanning without external components. Capacitive sensing is
configurable on each pin.
Additional System Resources
System resources provide additional capability useful to
complete systems. Additional resources are low voltage
detection and power on reset (POR).
The I2C slave provides 50, 100, or 400 kHz communication
over two wires.
Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels and the advanced POR circuit elimi-
nates the need for a system supervisor.
An internal 1.8V reference provides a stable internal reference
so that capacitive sensing functionality is not affected by minor
VDD changes.
I2C Interface
The two modes of operation for the I2C interface are:
Device register configuration and status read or write for
controller.
Command execution.
The I2C address is programmable during configuration. It can be
locked to prevent accidental change by setting a flag in a config-
uration register.
CapSense Express Software Tool
An easy to use software tool integrated with PSoC Express is
available for configuring and tuning CapSense Express devices.
Refer to the Application Note AN42137 for details of the software
tool.
CapSense Express Register Map
CapSense Express supports user configurable registers through
which the device functionality and parameters are configured.
For details, refer to CY8C201xx Register Reference document.
Electrical Specifications
Absolute Maximum Ratings
Parameter
Description
Min Typ Max Unit
Notes
TSTG
Storage temperature
–55 25 +100 °C Higher storage temperatures reduce
data retention time. Recommended
storage temperature is +25°C ± 25°C
(0°C to 50°C). Extended duration
storage temperatures above 65°C
degrade reliability.
TA
Ambient temperature with power
–40 – +85 ºC
applied
VDD
VIO
VIOZ
IMIO
ESD
Supply voltage on VDD relative to VSS –0.5
+6.0
V
DC input voltage
VSS – 0.5 – VDD + 0.5 V
DC voltage applied to tri-state
VSS – 0.5 – VDD + 0.5 V
Maximum current into any GPIO pin –25 – +50 mA
Electro static discharge voltage 2000 – – V Human body model ESD
LU Latch up current
– – 200 mA
Operating Temperature
Parameter
Description
TA Ambient temperature
TJ Junction temperature
Min Typ Max Unit
–40 – +85 °C
–40 – +100 °C
Notes
Document Number: 001-17346 Rev. *C
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CY8C20180
Package Diagram
Figure 4. 16L Chip On Lead 3 X 3 mm Package Outline (SAWN) - 001-09116 - (Pb-Free)
DIMENSIONS IN mm MIN.
MAX.
2.9
3.1 0.20 min
0.20 DIA TYP.
1
2
2.9
3.1
0.60 MAX
0.152 REF.
0.05 MAX
SEATING PLANE
1.5 (NOM)
2
1
PIN #1 ID
0.30
0.18
0.50
1.5
0.45
0.55
TOP VIEW
SIDE VIEW
BOTTOM VIEW
PART NO.
LG16A
LD16A
DESCRIPTION
LEAD-FREE
STANDARD
Figure 5. 16 - Pin (150-Mil) SOIC (51-85068)
JEDEC # MO-220
Package Weight: 0.014g
001-09116-*C
Document Number: 001-17346 Rev. *C
51-85068-*B
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