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DRPIC166X Schematic ( PDF Datasheet ) - Digital Core Design

Teilenummer DRPIC166X
Beschreibung High Performance Configurable 8-bit RISC Microcontroller
Hersteller Digital Core Design
Logo Digital Core Design Logo 




Gesamt 8 Seiten
DRPIC166X Datasheet, Funktion
www.DataSheet4U.com
DRPIC166X
High Performance Configurable
8-bit RISC Microcontroller
ver 2.15
OVERVIEW
The DRPIC166X is a low-cost, high per-
formance, 8-bit, fully static soft IP Core,
dedicated for operation with fast (typically on-
chip) dual ported memory. The core has been
designed with a special concern about low
power consumption.
DRPIC166X soft core is software-
compatible with the industry standard
PIC16C6X. It implements an enhanced
Harvard architecture (i.e. separate
instruction and data memories) with
independent address and data buses. The 14
bit program memory and 8-bit dual port data
memory allow instruction fetch and data
operations to occur simultaneously. The
advantage of this architecture is that
instruction fetch and memory transfers can be
overlapped by multi stage pipeline, so that the
next instruction can be fetched from program
memory while the current instruction is
executed with data from the data memory.
The DRPIC166X architecture is 4 times
faster compared to standard architecture. So
most instructions are executed within 1
system clock period, except the instructions
which directly operates on program counter
PC (GOTO, CALL, RETURN), this situation
require the pipeline to be cleared and
subsequently refilled. This operation takes
additional one clock cycle.
The DRPIC166X Microcontroller fits
perfectly in applications ranging from high-
All trademarks mentioned in this document
are trademarks of their respective owners.
speed automotive and appliance motor control
to low-power remote transmitters/receivers,
pointing devices and telecom processors.
Built-in power save mode make this IP perfect
for applications where power consumption is
critical.
DRPIC166X is delivered with fully automated
testbench and complete set of tests
allowing easy package validation at each
stage of SoC design flow
CPU FEATURES
Software compatible with industry standard
PIC16C6X
Pipelined Harvard architecture 4 times
faster compared to original implementation
35 – 14 bit wide instructions
Up to 512 bytes of internal Data Memory
Up to 64K bytes of Program Memory
Configurable hardware stack
Power saving SLEEP mode
Fully synthesizable, static synchronous
design with no internal tri-states
Technology independent HDL Source
Code
1.4 GHz virtual clock frequency in a 0.18u
technological process
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.






DRPIC166X Datasheet, Funktion
Owww.DataSheet4U.com P T I O N A L
PERIPHERALS
There are also available an optional
peripherals, not included in presented
DRPIC166X Microcontroller Core. The
optional peripherals, can be implemented in
microcontroller core upon customer request.
SPI – Master and Slave Serial Peripheral
Interface
Supports speeds up ¼ of system clock
Mode fault error
Write collision error
Software selectable polarity and phase of
serial clock SCK
System errors detection
Allows operation from a wide range of system
clock frequencies (build-in 5-bit timer)
Interrupt generation
I2C bus controller - Master
7-bit and 10-bit addressing modes
NORMAL, FAST, HIGH speeds
Multi-master systems supported
Clock arbitration and synchronization
User defined timings on I2C lines
Wide range of system clock frequencies
Interrupt generation
I2C bus controller - Slave
NORMAL speed 100 kbs
FAST speed 400 kbs
HIGH speed 3400 kbs
Wide range of system clock frequencies
User defined data setup time on I2C lines
Interrupt generation
PERFORMANCE
The following table gives a survey about
the Core area and performance in the
ALTERA® devices after Place & Route:
Device
CYCLONE
CYCLONE II
STRATIX
STRATIX II
STRATIX GX
APEX II
APEX20KC
APEX20KE
APEX20K
ACEX1K
FLEX10KE
Speed
grade
-6
-6
-5
-3
-5
-7
-7
-1
-1
-1
-1
Logic Cells
1654
1654
1655
1401
1655
1695
1695
1695
1695
1695
1695
Fmax
81 MHz
72 MHz
86 MHz
166 MHz
84 MHz
74 MHz
64 MHz
54 MHz
50 MHz
52 MHz
54 MHz
Core performance in ALTERA® devices
Area utilized by the each unit of DRPIC166X
core in vendor specific technologies is
summarized in table below.
Component
Area
[LC]
[FFs]
CPU*
904 296
Timer 0
60 29
Timer 1
81 30
Timer 2
90 34
USART
257 100
CCP1
111 32
Watchdog Timer
55 38
I/O Ports
96 64
Total area
1 654
625
*CPU – consisted of ALU, Control Unit, Bus Controller, Hardware Stack,
External INT pin Interrupt Controller, Extended interrupt controller,(512
Bytes RAM and 8kW of program memory)
Core components area utilization
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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