Datenblatt-pdf.com


ADP1752 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP1752
Beschreibung (ADP1752 / ADP1753) 800mA Low-Vin LDO Regulator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
ADP1752 Datasheet, Funktion
www.DataSheet4U.com
FEATURES
Maximum output current: 0.8 A
Input voltage range: 1.6 V to 3.6 V
Low shutdown current: <2 μA
Very low dropout voltage: 70 mV @ 0.8 A load
Initial accuracy: ±1%
Accuracy over line, load, and temperature: ±2%
7 fixed output voltage options with soft start
0.75 V to 2.5 V (ADP1752)
Adjustable output voltage option with soft start
0.75 V to 3.0 V (ADP1753)
High PSRR
65 dB @ 1 kHz
65 dB @ 10 kHz
54 dB @ 100 kHz
23 μV rms at 0.75 V output
Stable with small 4.7 μF ceramic output capacitor
Excellent load and line transient response
Current-limit and thermal overload protection
Power-good indicator
Logic-controlled enable
Reverse current protection
APPLICATIONS
Server computers
Memory components
Telecommunications equipment
Network equipment
DSP/FPGA/microprocessor supplies
Instrumentation equipment/data acquisition systems
GENERAL DESCRIPTION
The ADP1752/ADP1753 are low dropout (LDO) CMOS linear
regulators that operate from 1.6 V to 3.6 V and provide up to
800 mA of output current. These low VIN/VOUT LDOs are ideal
for regulation of nanometer FPGA geometries operating from
2.5 V down to 1.8 V I/O rails, and for powering core voltages
down to 0.75 V. Using an advanced proprietary architecture,
they provide high power supply rejection ratio (PSRR) and low
noise, and achieve excellent line and load transient response
with only a small 4.7 μF ceramic output capacitor.
The ADP1752 is available in seven fixed output voltage options.
The ADP1753 is the adjustable version, which allows output
0.8 A, Low VIN, Low Dropout
Linear Regulator
ADP1752/ADP1753
TYPICAL APPLICATION CIRCUITS
VIN = 1.8V
VOUT = 1.5V
4.7µF
100k
PG
16 15 14 13
VIN VIN VOUT VOUT
1 VIN
VOUT 12
2 VIN
3 VIN
ADP1752 VOUT 11
TOP VIEW
(Not to Scale) VOUT 10
4 EN
PG GND SS
5 67
SENSE 9
NC
8
4.7µF
10nF
VIN = 1.8V
Figure 1. ADP1752 with Fixed Output Voltage, 1.5 V
VOUT = 0.5V(1 + R1/R2)
4.7µF
100k
PG
16 15 14 13
VIN VIN VOUT VOUT
1 VIN
VOUT 12
2 VIN
3 VIN
ADP1753 VOUT 11
TOP VIEW
(Not to Scale) VOUT 10
4 EN
PG GND SS
567
ADJ 9
NC
8
4.7µF
R1
R2
10nF
Figure 2. ADP1753 with Adjustable Output Voltage, 0.75 V to 3.0 V
voltages that range from 0.75 V to 3.0 V via an external divider.
The ADP1752/ADP1753 allow an external soft start capacitor
to be connected to program the startup. A digital power-good
output allows power system monitors to check the health of the
output voltage.
The ADP1752/ADP1753 are available in a 16-lead, 4 mm × 4 mm
LFCSP, making them not only very compact solutions, but also
providing excellent thermal performance for applications that
require up to 800 mA of output current in a small, low profile
footprint.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.






ADP1752 Datasheet, Funktion
wwAwD.DPat1aS7he5e2t4/UA.coDmP1753
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VIN 1
VIN 2
VIN 3
EN 4
PIN 1
INDICATOR
ADP1752
TOP VIEW
(Not to Scale)
12 VOUT
11 VOUT
10 VOUT
9 SENSE
VIN 1
VIN 2
VIN 3
EN 4
PIN 1
INDICATOR
ADP1753
TOP VIEW
(Not to Scale)
12 VOUT
11 VOUT
10 VOUT
9 ADJ
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
Figure 3. ADP1752 Pin Configuration
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
Figure 4. ADP1753 Pin Configuration
Table 5. Pin Function Descriptions
ADP1752
Pin No.
ADP1753
Pin No.
Mnemonic
1, 2, 3, 15, 16 1, 2, 3, 15, 16 VIN
4 4 EN
5 5 PG
6 6 GND
7 7 SS
8 8 NC
9 N/A SENSE
N/A
10, 11, 12,
13, 14
17 (EPAD)
9
10, 11, 12,
13, 14
17 (EPAD)
ADJ
VOUT
Exposed
paddle
(EPAD)
Description
Regulator Input Supply. Bypass VIN to GND with a 4.7 μF or greater capacitor. Note that all
five VIN pins must be connected to the source.
Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For
automatic startup, connect EN to VIN.
Power Good. This open-drain output requires an external pull-up resistor to VIN. If the part is
in shutdown mode, current-limit mode, thermal shutdown, or if it falls below 90% of the
nominal output voltage, PG immediately transitions low.
Ground.
Soft Start. A capacitor connected to this pin determines the soft start time.
Not Connected. No internal connection.
Sense. This pin measures the actual output voltage at the load and feeds it to the error
amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop
between the regulator output and the load.
Adjust. A resistor divider from VOUT to ADJ sets the output voltage.
Regulated Output Voltage. Bypass VOUT to GND with a 4.7 μF or greater capacitor. Note that
all five VOUT pins must be connected to the load.
The exposed pad on the bottom of the LFCSP package enhances thermal performance and
is electrically connected to GND inside the package. It is recommended that the exposed
pad be connected to the ground plane on the board.
Rev. A | Page 6 of 20

6 Page









ADP1752 pdf, datenblatt
wwAwD.DPat1aS7he5e2t4/UA.coDmP1753
T EN
1
VOUT
2
500mV/DIV
VOUT = 1.5V
CIN = COUT = 4.7µF
CH1 2.0V BW
CH2 500mV BW M40µs A CH1
T 9.8%
920mV
Figure 27. VOUT Ramp-Up with Internal Soft Start
ADJUSTABLE OUTPUT VOLTAGE (ADP1753)
The output voltage of the ADP1753 can be set over a 0.75 V to
3.0 V range. The output voltage is set by connecting a resistive
voltage divider from VOUT to ADJ. The output voltage is calcu-
lated using the following equation:
VOUT = 0.5 V × (1 + R1/R2)
(2)
where:
R1 is the resistor from VOUT to ADJ.
R2 is the resistor from ADJ to GND.
The maximum bias current into ADJ is 150 nA. Therefore, to
achieve less than 0.5% error due to the bias current, use values
less than 60 kΩ for R2.
ENABLE FEATURE
The ADP1752/ADP1753 use the EN pin to enable and disable
the VOUT pin under normal operating conditions. As shown in
Figure 28, when a rising voltage on EN crosses the active
threshold, VOUT turns on. When a falling voltage on EN
crosses the inactive threshold, VOUT turns off.
T
EN
VOUT
The EN pin active/inactive thresholds are derived from the VIN
voltage. Therefore, these thresholds vary with changing input
voltage. Figure 29 shows typical EN active/inactive thresholds
when the input voltage varies from 1.6 V to 3.6 V.
1.1
1.0
0.9
EN ACTIVE
0.8
EN INACTIVE
0.7
0.6
0.5
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
INPUT VOLTAGE (V)
Figure 29. Typical EN Pin Thresholds vs. Input Voltage
POWER-GOOD FEATURE
The ADP1752/ADP1753 provide a power-good pin, PG, to
indicate the status of the output. This open-drain output
requires an external pull-up resistor to VIN. If the part is in
shutdown, in current limit mode, in thermal shutdown, or if it
falls below 90% of the nominal output voltage, PG immediately
transitions low. During soft start, the rising threshold of the
power-good signal is 93.5% of the nominal output voltage.
The open-drain output is held low when the ADP1752/ADP1753
have sufficient input voltage to turn on the internal PG transistor.
An optional soft start delay can be detected. The PG transistor
is terminated via a pull-up resistor to VOUT or VIN.
Power-good accuracy is 93.5% of the nominal regulator output
voltage when this voltage is rising, with a 90% trip point when
this voltage is falling.
Regulator input voltage brownouts or glitches trigger a power
no-good if VOUT falls below 90%.
A normal power-down triggers a power no-good when VOUT
drops below 90%.
21
500mV/DIV
VOUT = 1.5V
CIN = COUT = 4.7µF
CH1 500mV BW CH2 500mV BW M2.0ms A CH1
T 29.6%
1.05V
Figure 28. Typical EN Pin Operation
As shown in Figure 28, the EN pin has hysteresis built in. This
hysteresis prevents on/off oscillations that can occur due to
noise on the EN pin as it passes through the threshold points.
Rev. A | Page 12 of 20

12 Page





SeitenGesamt 20 Seiten
PDF Download[ ADP1752 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
ADP1752(ADP1752 / ADP1753) 800mA Low-Vin LDO RegulatorAnalog Devices
Analog Devices
ADP1753(ADP1752 / ADP1753) 800mA Low-Vin LDO RegulatorAnalog Devices
Analog Devices
ADP1754Low Dropout Linear RegulatorAnalog Devices
Analog Devices
ADP1755Low Dropout Linear RegulatorAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche