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PDF ACS761ELF-20B Data sheet ( Hoja de datos )
| Número de pieza | ACS761ELF-20B | |
| Descripción | 12V High-Side Hot-Swap Hall Effect Based Current Monitor | |
| Fabricantes | Allegro Micro Systems | |
| Logotipo |  |
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ACS761ELF-20B
12 V High-Side Hot-Swap Hall Effect Based Current Monitor
Features and Benefits
▪ Hall-effect current monitor—no external sense resistor required
▪ PGOOD and ¯P¯¯G¯¯¯O¯¯O¯¯¯D¯ indication
▪ Analog output voltage (factory trimmed for gain and offset)
proportional to applied current
▪ External high-side FET gate drive
▪ 240V*A power fault protection with user-selectable delay
▪ Overcurrent fault protection with user-selectable delay
▪ Fault protection isolates failed supply from output in < 2 μs
▪ 1.5 mΩ internal conductor resistance
▪ Active low latched Fault indicator output signal
▪ User controlled soft start / hot-swap function
▪ Logic enable input pin
▪ 10.8 to 13.2 V, single-supply operation
▪ 2 kV ESD protection for all pins
Package: 24 pin QSOP (suffix LF)
Description
The ACS761 combines Allegro® Hall-effect current sense
technology with a hot-swap controller resulting in a more
efficient integrated controller for 12 V applications. By
eliminating the need for a shunt resistor, the I2R losses in the
power path are reduced.
When the ACS761 is externally enabled, and the voltage rail is
above the internal UVLO threshold, the internal charge pump
drives the gate of the external FET. When the load voltage
reaches its target value PGOOD is asserted high. When a fault
is detected, the gate is disabled while simultaneously alerting
the application that a fault has occurred.
The integrated protection in the ACS761 incorporates three
levels of fault protection, which includes a Power Fault with
user-selectable delay, an Overcurrent Fault threshold with user-
selectable delay, and Short Circuit protection, which disables
the gate in less than 2 μs. These faults are indicated to the
host system via the Fault pin and are cleared upon reasserting
enable high.
Approximate Scale
Typical Application
Enable
1
2
IP 3
4
CIN RV1
5
6
REN
7
CEN
8
VOUT 9
10
CG
COCD
COPD
11
12
24
IP+ IP–
23
IP+ IP–
22
IP+ IP–
21
IP+
ACS761
IP–
20
IP+ IP–
19
IP+ IP–
18
EN GATE
17
VIOUT
GND
16
NC PGOOD
15
CG FB+
14
OCDLY
PGOOD
13
OPDLY
FAULT
S1 VLOAD
CLOAD
RG
RFB
3.3 V
100
kΩ
RS1
100 kΩ
RFAULT
100 kΩ
761ELF20B-DS, Rev. 2
1 page  
wwAw.CDaStaS7he6e1t4UE.cLomF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor
OPERATING CHARACTERISTICS valid at VCC = 12 V, TA = 0°C to 85°C, unless otherwise noted
Characteristic
Symbol
Test Conditions
General Electrical Characteristics
Source Current
Linear Sensing Range
Primary Conductor Resistance
Supply Voltage
Supply Current
Undervoltage Lockout (UVLO)
ISOURCE
IP
RPRIMARY
VCC
ICC
VUVLOH
VUVLOL
UVLO Delay to Chip Enable/ Disable
tUVLOE
tUVLOD
FB+ Input Resistance
RFB
Current Sense Performance Characteristics
VIOUT Analog Output Propagation
Time
tPROP
VIOUT Analog Output 10-90% Rise
Time
tr
VIOUT Load Capacitance
VIOUT Load Resistance
CLOAD
RLOAD
VIOUT Analog Signal Bandwidth1
f3dB
TA = 25°C, VIOUT connected to GND
Current flows from IP+ to IP- pins
TA = 25°C
Voltage applied to IP+ pins
VCC rising and CG pin current source turns on, EN pin = high
VCC falling and CG pin current source turns off, EN pin = high
Enabling, measured from rising VCC > VUVLOH to
VGATE > 1 V, EN pin = high
Disabling, measured from falling VCC < VUVLOL to
VGATE < 1 V, EN pin = high
TA = 25°C
TA = 25°C, IP = 0 →20 A, capacitance from VIOUT to GND
= 100 pF
TA = 25°C, IP = 0 →20 A, capacitance from VIOUT to GND
= 100 pF
–3 dB, Ip = 10 A peak-to-peak, TA = 25°C, no external device
filter, capacitance from VIOUT to GND = 100 pF
VIOUT Analog Signal Sensitivity
Sens
TA = 25°C
Over full ambient operating temperature range
Sensitivity Slope Over Temperature
VIOUT Analog Noise Level2
VIOUT Analog Nonlinearity
∆SensTA
VNOISE(PP)
ELIN
TA = 0°C to 25°C
TA = 25°C to 85°C
Mean peak-to-peak, TA = 25°C, 50 kHz external device filter
Over full ambient operating temperature range and linear
sensing range
Zero Current Output Voltage
Zero Current Output Slope Over
Temperature
Output Voltage Saturation3
VIOUT Total Error % of IP
VIOUT(Q)
∆IOUT(Q)TA
VOL
VOH
ETOT
TA = 0°C to 85°C
TA = 0°C to 25°C
TA = 25°C to 85°C
TA = 25°C
TA = 25°C
TA = 25°C, IP = 20 A
TA = 0°C to 85°C, IP = 20 A
Min.
–
0
–
10.8
–
–
7.0
–
–
–
–
–
–
20
–
–
63
–
–
–
–
0.18
–
–
–
–
–
–4
Typ. Max. Units
250 –
– 55
1.5 –
12 13.2
8 10.5
– 10.5
––
700 1100
μA
A
mΩ
V
mA
V
V
μs
1 2.5
240 –
μs
kΩ
2 – μs
5
–
–
50
65
–
0.042
0.027
20
±0.5
0.2
–0.148
–0.057
0.15
3.71
<±1.0
–
– μs
1 nF
– kΩ
– kHz
– mV/A
69 mV/A
– mV/A/°C
– mV/A/°C
– mV
±1 %
0.22 V
– mV/°C
– mV/°C
–V
–V
–%
4%
Continued on the next page…
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
5 Page 
wwAw.CDaStaS7he6et14UE.cLomF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor
sources). The voltages on each delay pin continues to increase
with a constant slope until:
• either the OPDLY or the OCDLY pin voltage reaches a thresh-
old of 3.85 V (if this occurs, the ¯F¯A¯¯U¯¯L¯¯T¯ signal is latched in the
low state), or
• the current load of the system falls below 20 A for the OPDLY
pin and 40 A for the OCDLY pin.
In figure 2 a short circuit fault event is detected at t40A_F . At
this time, the ¯F¯A¯¯U¯¯L¯¯T¯ signal transitions to the low state and the
GATE pin is pulled to ground. The ¯F¯A¯¯U¯¯L¯¯T¯ state is latched and
the chip will pull down the GATE voltage until the EN pin of the
ACS761 transitions to the low state and then back to the high
state. As shown in the timing diagram, certain ACS761 signals
(the ¯F¯A¯¯U¯¯L¯¯T¯ signal and the OCDLY pin voltage) are reset when
the EN pin transitions to the low state. These signals are reset in
order to guarantee normal device operation (soft start and fault
monitoring) when the EN signal transitions back to the high state.
Hard Short Circuit Fault Operation
The timing diagram in figure 3 specifically shows characteristic
operation of the ACS761 when the device is powered on (via
the EN pin) and a 50 m short circuit is present from load side
of the external MOSFET, S1, to ground. In figure 3 the system
power supply bus reaches the nominal steady state level of 12 V
before the EN pin of the ACS761 transitions to the high state at
time tEN1. The voltage on the GATE pin increases with a posi-
tive slope after the EN pin transitions to the high state. The ramp
rate of the GATE pin is controlled by the value of the capacitor
connected to the CG pin. In the example shown below a small
capacitor is connected to the CG pin and the pin ramps to 5.5 V
in < 10 s.
In panel A of figure 3, the device is enabled into a 50 m short
circuit. Therefore, as the GATE voltage increases the cur-
rent through the external MOSFET increases at a rapid rate.
In this example, it is assumed that there is no capacitor on the
OCDLY pin. When the current through the MOSFET exceeds
0.2 V
5.25 V
40 A
0V
3.3 V
≈0V
0V
0V
0V
3.85 V
Threshold
0V
12 V
tEN1
t40A_F
tGATE_LOW
VIOUT Voltage
Load Current /IP
GATE Voltage
FAULT
EN
CG Pin Voltage
VLOAD to Load
OPDLY Pin Voltage
OCDLY Pin Voltage
Voltage on IP+ Pins
1.648 V
22 V
0.4 V
3.3 V
5.5 V
12 V
5.5 V
tRESET
Time
(A)
0.2 V
130 A
40 A
0A
0V
3.3 V
≈0V
0V
0V
3.85 V
Threshold
0V
3.85 V
Threshold
0V
12 V
tEN1
t40A_F
t130A_F
tGATE_LOW
VIOUT Voltage
1.648 V
Load Current /IP
GATE Voltage
FAULT
EN
19.2 A
22 V
0.4 V
3.3 V
CG Pin Voltage
VLOAD to Load
5.5 V
12 V
OPDLY Pin Voltage
OCDLY Pin Voltage
Voltage on IP+ Pins
tRESET
<2 μs
Time
(B)
Figure 3. (A) Timing Diagram for a 50 mΩ Short Circuit from VLOAD to GND; (B) Timing Diagram for a 50 mΩ Short Circuit
from VLOAD to GND, capacitor COCD with high rating connected.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ACS761ELF-20B.PDF ] | |
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